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Firmware Architect

TylSemi, Inc. – San Jose, California, United States

About this position

About TYLsemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds chiplet infrastructure IP—the IO, power delivery, and interconnect building blocks—that makes AI/HPC systems actually work at scale.

This isn't a nice‑to‑have. It's the critical path.

Why Now / The Market Window

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote‑Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location.
• India team: Building a world‑class design center in Bangalore.

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Reasons to Join

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de‑risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click‑through rate. You're building the silicon infrastructure that powers AI.

READY TO JOIN?

But if you're the kind of person who wants to take the shot, we'd love to talk.

What you’ll do Firmware & Embedded Software Architecture Leadership

Own the end‑to‑end firmware/embedded‑software architecture for TYLsemi chiplets. Define the firmware/hardware interface together with the Chip Architects for a seamless HW‑to‑SW handoff; define the MCU subsystem (MCU SS) architecture from the firmware point of view; and define the chip's debug interface and debug features.

On‑die: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address‑translation (NTB/ATT) setup, MSI‑X and AER handling, reset/FLR, power management, telemetry, and in‑field firmware update.

Host‑side: kernel drivers, the device‑virtualization/transparency shim (synthetic PCIe device, VFIO‑mdev‑class), management libraries/APIs, and IOMMU (VT‑d/SMMU) coordination. Define the hardware/software boundary with architecture and RTL — datapath (credit, ordering, merge/split, address‑translation execution) in RTL; control plane in firmware — and own register maps and UCIe sideband/mailbox protocols. Define a unified flow for firmware development and DV test cases, with a single source of truth shared across firmware and DV (register models, stimulus, and sequences), and drive HW/SW co‑verification. Stay hands‑on through first silicon.

Bring‑up, Methodology & Quality

Drive pre‑silicon firmware and host‑software development on emulation, and virtual platforms, and lead post‑silicon bring‑up and debug. Stand up the firmware engineering infrastructure: CI, automated and HIL testing, requirement traceability, secure‑development practices (secure boot, attestation, key management), and the RAS/error‑handling and fault‑attribution strategy. Define firmware release, quality, and security criteria across products and customers.

Cross‑functional & Customer Collaboration

Be the technical bridge between firmware/software and architecture, RTL, DV, PHY/IP vendors and program management — bringing software feasibility into hardware decisions early. Work directly with customers: compute‑SoC partners on PCIe/CXL enablement, ATE/SLT integrators on the firmware and management libraries.

Technical Leadership & Ownership

Set technical direction, roadmap, and clear subsystem ownership (boot/security, PCIe/CXL management, host drivers and virtualization, RAS/telemetry).

What We're Looking For

• BS/MS in Electrical /Computer Engineering or Computer Science
• 12+ years of embedded firmware development, with at least 5 years in silicon‑level bring‑up and validation of high‑speed interface IPs
• Working knowledge of design verification (DV) and HW/SW co‑simulation / co‑verification flows, and the ability to define a unified firmware + DV test flow with a single source of truth
• Expert‑level C and assembly for resource‑constrained embedded CPUs (RISC‑V or Arm Cortex‑M/R class); strong debugging skills using JTAG/OpenOCD, trace, and logic analysers
• Deep PCIe expertise: link‑training state machine, equalization, speed‑change sequences, LTSSM register‑level behaviour
• Hands‑on experience with HPC compute SoC firmware ecosystems — UEFI/BIOS bring‑up, ACPI table authoring, SMBus/I2C/MCTP platform management, VT‑d/IOMMU configuration — on HPC platforms
• Solid understanding of x86 server platform boot flow: PCIe enumeration, ROM interaction, and PCIe error‑recovery paths (AER, DPC)
• Experience with secure‑boot architectures, code‑signing flows, and OTA update mechanisms on embedded targets
• Comfortable working at the hardware‑software boundary: reading RTL, memory‑mapped register specs, and waveforms from simulation or a logic analyser

Good To Have

• CXL 2.0/3.0 firmware experience: HDM decoder programming, CXL IDE, DVSEC, BISnp coordination
• UCIe / die‑to‑die sideband firmware experience (RDI/FDI parameter negotiation, sideband messaging)
• SPDM (DSP0274) and CMA device‑attestation implementation experience
• Familiarity with PLDM for firmware update (DSP0267) and platform telemetry (DSP0248)
• ATE scripting background — Teradyne UltraFLEX/Advantest T2000 board‑level bring‑up scripts
• Exposure to chiplet packaging concepts (UCIe, EMIB, CoWoS) and multi‑die power‑sequencing considerations
• Kernel‑mode driver or UEFI DXE driver development experience

The pay range for this role is: 150,000 – 300,000 USD per year (San Jose (HQ))