Grid
Grid

60 Grid Hardware Engineer Jobs Hiring Near You

The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Power grid planning and analysis * Clock tree synthesis (CTS) strategy integration * Enable ...

The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Power grid planning and analysis * Clock tree synthesis (CTS) strategy integration * Enable ...

The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Power grid planning and analysis * Clock tree synthesis (CTS) strategy integration * Enable ...

The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Power grid planning and analysis * Clock tree synthesis (CTS) strategy integration * Enable ...

Showing results 21-40

EDA Tools Hardware Engineer

Intel

Folsom, CA

$141K - $269K/yr

Full-time

Medical, Retirement, PTO

Re-posted 28 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers


Job description

Job Details:Job Description: 

The Role and Impact
Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.
Key Responsibilities

  • Full Chip Implementation Flow Development

  • Develop and maintain full-chip physical implementation flows including:

  • Floor planning and partitioning strategies

  • Hierarchical block integration

  • Chip-level placement and routing coordination

  • Power grid planning and analysis

  • Clock tree synthesis (CTS) strategy integration

  • Enable scalable SoC assembly flows for multi-block and multi-power domain designs.

  • Define methodology for hierarchical design reuse and integration

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience

  • Physical design fundamentals (I.e. placement, routing)

  • Clock tree synthesis (CTS)

  • Full-chip integration methodologies using Innovus

Preferred Qualifications

  • Static timing analysis (STA)

  • Power grid design and IR drop concepts

  • Experience with large SoC or multi-block design implementation flows

  • Experience scripting and automation skills in Linux environments

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, California, Folsom, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968