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Wafer Sort Test Jobs (NOW HIRING)

Samsung Electronics

Wafer Sort Test Engineer

Austin, TX · On-site

$106K - $206K/yr

Wafer Sort test programs will range from LOGIC / SRAM test vehicles to complex full product testing at wafer sort (SoC, RF, Memory, etc applications). * Prior experience in designing, developing, and ...

Astera Labs

Principal Test Engineer

San Jose, CA

$209K - $230K/yr

Tester platform selection, design, and development of ATE hardware for wafer sort and final test. * Familiar with high-speed load board design techniques. * Proven track record of implementing ATE ...

Astera Labs

Principal Test Engineer

San Jose, CA · On-site

$209K - $230K/yr

Tester platform selection, design, and development of ATE hardware for wafer sort and final test. * Familiar with high-speed load board design techniques. * Proven track record of implementing ATE ...

ISE LABS INC AND SUBSIDIARY

Test Floor Lead

Fremont, CA

$27 - $30/hr

Pick and place handlers, loading test programs on testers, scanner equipment, hand/bench test equipment, wafer sort probers, etc. * Accurately enter binning and yield data into the Test Database by ...

Marvell

Test Engineer - ATE & SLT

Santa Clara, CA · On-site

Develop characterization, production, and wafer sort test programs on the Advantest 93K tester. Create all the documentation for detail test plans and test methodologies to meet product ...

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How much do wafer sort test jobs pay per hour?

As of Jun 4, 2026, the average hourly pay for wafer sort test in the United States is $19.16, according to ZipRecruiter salary data. Most workers in this role earn between $17.07 and $20.67 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Wafer Sort Test Engineer, and why are they important?

To excel as a Wafer Sort Test Engineer, you need a solid background in electrical engineering, semiconductor physics, and experience with automated test equipment (ATE) and wafer probing processes. Familiarity with programming languages such as Python or C++, test data analysis tools, and industry certifications like ISTQB or Six Sigma are often required. Strong analytical thinking, attention to detail, and effective communication skills set outstanding candidates apart. These abilities ensure accurate testing, efficient problem-solving, and high-quality semiconductor products in a rapidly evolving industry.

What are some common challenges faced in a Wafer Sort Test role and how can they be addressed?

Professionals in Wafer Sort Test roles often encounter challenges such as handling high-volume testing schedules, quickly diagnosing yield issues, and ensuring data accuracy under tight deadlines. Effective communication with process engineers and equipment maintenance teams is crucial to swiftly resolve equipment or process-related problems. Staying organized, leveraging automated test systems, and proactively participating in cross-functional meetings can help address these challenges and contribute to smoother operations.

What is a Wafer Sort Test?

A Wafer Sort Test is a process used in semiconductor manufacturing to electrically test each individual die on a silicon wafer before it is cut and packaged. This testing identifies defective chips early in the production process, which helps improve overall yield and reduce costs. The test is performed using specialized equipment called a wafer prober and test system, and the results are used to map out good and bad dies for further processing.

What is the difference between Wafer Sort Test vs Device Test Engineer?

AspectWafer Sort TestDevice Test Engineer
CredentialsTechnical certifications, associate degrees in electronics or semiconductor technologyEngineering degree, often in electrical or electronics engineering
Work EnvironmentCleanroom environments focused on wafer testingLaboratories or production floors testing finished devices
Industry UsagePrimarily in semiconductor manufacturing plantsIn semiconductor companies, testing finished or packaged devices
Common Search/ComparisonOften compared for roles in semiconductor testing processesRelated but focuses on device-level testing after wafer testing

Wafer Sort Test involves testing semiconductor wafers during manufacturing to identify functional chips before dicing. Device Test Engineers focus on testing individual semiconductor devices after packaging. Both roles require technical skills and work in semiconductor environments, but they differ in testing stage and scope.

Infographic showing various Wafer Sort Test job openings in the United States as of May 2026, with employment types broken down into 13% Locum Tenens, 16% Internship, 46% Full Time, 7% Temporary, 11% Contract, and 7% Nights. Highlights an 99% Physical, and 1% Remote job distribution, with an average salary of $39,852 per year, or $19.2 per hour.
Wafer Sort Test Engineer

Wafer Sort Test Engineer

Samsung Electronics Co., Ltd.

Austin, TX • On-site

$106K - $206K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted just now

Samsung Electronics rating

7.0

Company rating: 7.0 out of 10

Based on 48 frontline employees who took The Breakroom Quiz

104th of 139 rated electronics manufacturers

Job description

About Samsung Austin Semiconductor
Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At SAS, we are Innovating Today to Power the Devices of Tomorrow.
Come innovate with us!
Position Summary
In your role as a Test Engineer at Samsung, you will directly impact upcoming process technologies by providing feedback for Logic & SRAM test vehicles to process architecture teams.
Additionally, you can expand your experience by evaluating process BKMs on various high volume manufacturing products that defines Samsung's competitive edge.
Role and Responsibilities
Here's what you'll be responsible for:
  • Implementing testing solutions for Multi Product Wafer (MPW) Test Vehicles and upcoming new products for Samsung's latest process technology.
  • Driving Innovation in Test Engineering within a high-volume production testing on the Advantest V93000 and/or UltraFLEX test platforms to provide technical execution in developing robust, scalable, and optimized test infrastructure.
  • Designing / verifying hardware, including probe cards and interface boards to support New Product / Technology Introduction and accelerate time to market for our end customers; ensuring tester licensing and hardware resources to fit product needs.
  • Adding/Updating Test patterns, verify across process, voltage, and temperature. Implement Vmin/Vmax data collection for various products.
  • Implementing wafer level SCAN diagnostics and SRAM Bitmap data, post process and analysis.
  • Debugging tool / probing card issues, managing test program revisions, updating prober interface that interact with internal systems.

Skills and Qualifications
Here's what you'll need:
  • B.S / M.S in Electrical Engineering or equivalent experience
  • 10+ years of Test Engineering with Advantest V93K and/or UltraFLEX test platforms. Wafer Sort test programs will range from LOGIC / SRAM test vehicles to complex full product testing at wafer sort (SoC, RF, Memory, etc applications).
  • Prior experience in designing, developing, and deploying scalable test infrastructure (hardware and software) in high-volume manufacturing (HVM) environment. Familiarity with TEL prober and driver communication. Coding & scripting experience needed for debug purposes
  • Demonstrated ability to serve as a technical lead, mentor junior engineers, and drive cross-functional alignment between Design, Product, Test, and Manufacturing teams. Excellent written and verbal communication skills.

All positions at Samsung Austin Semiconductor are 5 days onsite.
The current base salary range for this role is between $106,000 - $206,000. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance.
Total Rewards
At Samsung SAS, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.
We offer a comprehensive benefits package, including:
  • Medical, dental, and vision insurance
  • Life insurance and 401(k) matching with immediate vesting
  • Onsite café(s) and workout facilities
  • Paid maternity and paternity leave
  • Paid time off (PTO) + 2 personal holidays and 10 regular holidays
  • Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.
All positions at SAS are full-time on-site.
U.S. Export Control Compliance
This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.
Trade Secrets Notice
By submitting an application, you agree not to disclose to Samsung-or encourage Samsung to use-any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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