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Wafer Sort Test Jobs (NOW HIRING)

Etched

Product Engineer, Silicon Validation

San Jose, CA · On-site

$2K/mo

Experience managing wafer sort and final test across multiple advanced process nodes * GPU, HPC, or AI accelerator chip testing background with production scale results * HBM or high-speed memory ...

Astera Labs

Lead Product Engineer

San Jose, CA · On-site

Production Test Development * Develop and optimize ATE test programs for RF and high-speed I/O parametric testing * Define test coverage strategies that balance quality, cost, and throughput for ...

Altera

Product Development Engineer

San Jose, CA · On-site

$142K - $206K/yr

We support wafer yield ramp and fab process optimization in early production stage for wafer Sort and Class yield thru systematic test data analysis to isolate and mitigate defects and failures. We ...

Altera

Product Development Engineer

San Jose, CA · On-site

$142K - $206K/yr

We support wafer yield ramp and fab process optimization in early production stage for wafer Sort and Class yield thru systematic test data analysis to isolate and mitigate defects and failures. We ...

Integra Technologies.

Account Manager

Wichita, KS · On-site

Sell full back-end semiconductor services starting from wafer sort, thinning and dicing through die-attach, wire-bond, package sealing and final test. * Where possible, cross sell other Micross ...

Marvell

Principal Test Engineer

Santa Clara, CA · On-site

As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Your work ...

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Wafer Sort Test information

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How much do wafer sort test jobs pay per hour?

As of Jun 4, 2026, the average hourly pay for wafer sort test in the United States is $19.16, according to ZipRecruiter salary data. Most workers in this role earn between $17.07 and $20.67 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Wafer Sort Test Engineer, and why are they important?

To excel as a Wafer Sort Test Engineer, you need a solid background in electrical engineering, semiconductor physics, and experience with automated test equipment (ATE) and wafer probing processes. Familiarity with programming languages such as Python or C++, test data analysis tools, and industry certifications like ISTQB or Six Sigma are often required. Strong analytical thinking, attention to detail, and effective communication skills set outstanding candidates apart. These abilities ensure accurate testing, efficient problem-solving, and high-quality semiconductor products in a rapidly evolving industry.

What are some common challenges faced in a Wafer Sort Test role and how can they be addressed?

Professionals in Wafer Sort Test roles often encounter challenges such as handling high-volume testing schedules, quickly diagnosing yield issues, and ensuring data accuracy under tight deadlines. Effective communication with process engineers and equipment maintenance teams is crucial to swiftly resolve equipment or process-related problems. Staying organized, leveraging automated test systems, and proactively participating in cross-functional meetings can help address these challenges and contribute to smoother operations.

What is a Wafer Sort Test?

A Wafer Sort Test is a process used in semiconductor manufacturing to electrically test each individual die on a silicon wafer before it is cut and packaged. This testing identifies defective chips early in the production process, which helps improve overall yield and reduce costs. The test is performed using specialized equipment called a wafer prober and test system, and the results are used to map out good and bad dies for further processing.

What is the difference between Wafer Sort Test vs Device Test Engineer?

AspectWafer Sort TestDevice Test Engineer
CredentialsTechnical certifications, associate degrees in electronics or semiconductor technologyEngineering degree, often in electrical or electronics engineering
Work EnvironmentCleanroom environments focused on wafer testingLaboratories or production floors testing finished devices
Industry UsagePrimarily in semiconductor manufacturing plantsIn semiconductor companies, testing finished or packaged devices
Common Search/ComparisonOften compared for roles in semiconductor testing processesRelated but focuses on device-level testing after wafer testing

Wafer Sort Test involves testing semiconductor wafers during manufacturing to identify functional chips before dicing. Device Test Engineers focus on testing individual semiconductor devices after packaging. Both roles require technical skills and work in semiconductor environments, but they differ in testing stage and scope.

Infographic showing various Wafer Sort Test job openings in the United States as of May 2026, with employment types broken down into 13% Locum Tenens, 16% Internship, 46% Full Time, 7% Temporary, 11% Contract, and 7% Nights. Highlights an 99% Physical, and 1% Remote job distribution, with an average salary of $39,852 per year, or $19.2 per hour.

Product Engineer, Silicon Validation

Etched

San Jose, CA • On-site

$2K/mo

Full-time

Medical, Dental, Vision

Posted 29 days ago

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking an experienced Product Engineer to lead silicon validation, test program

development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions.

Key Responsibilities

  • Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting

  • Lead test cost optimization efforts while maintaining quality standards

  • Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs

  • Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods

  • Establish and track key quality metrics including DPPM and test escapes

  • Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams

  • Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals

  • Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing

  • Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods

  • Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs

  • Manage relationships with test vendors, OSAT partners, and foundry partners

You may be a good fit if you have (Must-have qualifications)

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

  • 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors

  • Proven track record in yield optimization and DPPM reduction with quantifiable results

  • Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation

  • High-volume manufacturing test experience with demonstrated production scale results

  • Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus

  • Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques

Strong candidates may also have experience with (Nice-to-have qualifications)

  • Experience developing and optimizing ATE test programs for wafer sort and final test on

    Advantest V93K platforms

  • Experience managing wafer sort and final test across multiple advanced process nodes

  • GPU, HPC, or AI accelerator chip testing background with production scale results

  • HBM or high-speed memory interface testing and characterization experience

  • Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites

  • Driving significant cost reduction initiatives

  • Multi-site parallel testing strategies and test time optimization for large-format dies

  • Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation

  • Cross-functional leadership in silicon bring-up and manufacturing ramp

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2k per month for those living within walking distance of the office

  • Relocation support for those moving to San Jose (Santana Row)

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch and dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.