Job Summary:
Cadence is a technology company focused on developing leaders and innovators in the tech industry. The role involves enhancing existing tools' architecture for timing analysis and leveraging machine learning to improve EDA solutions.
Responsibilities:
• Enhance and expand existing tools' architecture to cover timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.
Qualifications:
Required:
• 8+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
• Hardcore C++ knowledge, particularly in a Linux environment.
• Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
• Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.
• Experience with quality and software processes.
• Proficiency in designing data structures, algorithms, and software engineering principles.
• Ability to analyze transistor or gate-level schematics.
• BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.
Preferred:
• Experience in development of circuit simulation or library characterization programs.
• Understanding of SPICE simulation transistor models at a high level.
• Experience with distributed programming, database design, and cloud APIs for distributed computing.
Company:
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Founded in 1988, the company is headquartered in San Jose, USA, with a team of 10001+ employees. The company is currently Late Stage.