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Timing Jobs (NOW HIRING)

Altera Corporation

Timing Engineer

San Jose, CA · On-site

$118K - $172K/yr

About the Role Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will lead timing activities for a subsystem, partnering closely with the Design ...

Altera

Timing Engineer

San Jose, CA · On-site

$118K - $172K/yr

About the Role Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will lead timing activities for a subsystem, partnering closely with the Design ...

Apple

Timing Design Engineer

Melbourne, FL · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Waltham, MA · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

San Diego, CA · On-site

We have an opportunity for a results-oriented and outstandingly hardworking Timing Design Engineer. As a member of our multifaceted group, you will have the outstanding and phenomenal opportunity to ...

Apple

Timing Design Engineer

Cupertino, CA · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Austin, TX · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Waltham, MA · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Etched

ASIC Timing Engineer

Cupertino, CA

$2.0K/mo

ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Austin, TX

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Cupertino, CA · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

City of New York

Timing Specialist

Queens, NY

Responsibilities include conducting field investigations and implementing timing changes to improve operational efficiency and safety for both vehicle and pedestrian traffic. The candidate will ...

Etched

ASIC Timing Engineer

Cupertino, CA · On-site

$2.0K/mo

ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Austin, TX · On-site

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

Beaverton, OR

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

Apple

Timing Design Engineer

San Diego, CA · On-site

$122K - $214K/yr

Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to ...

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All JobsTiming Jobs

Timing information

What is a timing job?

Timing jobs typically refer to roles responsible for the measurement and management of time in various contexts, such as sporting events, manufacturing processes, or broadcasting. These professionals ensure accurate tracking and reporting of time intervals, which is critical for fairness, efficiency, and record-keeping. Timing professionals may use specialized equipment and software to capture precise timings, analyze results, and often work under strict guidelines. They play an essential role in events like marathons, motorsports, or other competitions where exact timing is crucial.

What are some common challenges faced by professionals working in timing roles within engineering or broadcast environments?

Professionals in timing roles, such as timing engineers or broadcast timing operators, often face challenges related to maintaining precise synchronization across complex systems. Handling discrepancies caused by equipment drift, network latency, or signal interruptions requires strong problem-solving skills and attention to detail. Additionally, collaborating with cross-functional teams—such as engineers, IT specialists, or production staff—to quickly identify and resolve timing issues is essential for smooth operations. Staying current with evolving timing technologies and standards is also crucial for long-term success in this field.

What are the key skills and qualifications needed to thrive as a timing technician, and why are they important?

To thrive as a Timing Technician, you need a strong understanding of timing systems, electronics, and event coordination, typically supported by technical training or relevant certifications. Familiarity with industry-standard timing software (such as RaceResult or ChronoTrack), RFID technology, and troubleshooting hardware is essential. Attention to detail, problem-solving abilities, and effective communication are key soft skills that distinguish top performers. These skills ensure precise event timing, smooth operations, and accurate results, which are crucial for successful athletic competitions and races.

What is the difference between Timing vs Scheduling?

AspectTimingScheduling
Primary FocusDetermining the optimal time for tasks or eventsPlanning and arranging tasks or events in a specific order
Work EnvironmentOften used in project management, manufacturing, and event planningCommon in project management, healthcare, and operations
Required CredentialsKnowledge of time management, basic technical skillsOrganizational skills, project management tools

Timing focuses on identifying the best moments to perform tasks, while scheduling involves creating a detailed plan of when tasks will occur. Both are essential for efficient project execution but serve different purposes in the workflow.

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What states have the most Timing jobs?

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What job categories do people searching Timing jobs look for?

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Timing jobs near you
Infographic showing various Timing job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 79% Full Time, 16% Part Time, 1% Temporary, 2% Contract, and 1% Nights. Highlights an 83% Physical, 3% Hybrid, and 14% Remote job distribution.

Timing Engineer

San Jose, CA • On-site

Altera Corporation
Business Management Consulting • 1 - 5K employees
Learn more about Altera Corporationexternal

$118K - $172K/yr

Full-time

Posted 23 days ago

Job description

Job Details:
Job Description:
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will lead timing activities for a subsystem, partnering closely with the Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through final sign-off.
The ideal candidate brings strong expertise in static timing analysis (STA), timing constraints, and timing closure methodologies, with experience working on advanced process technologies. You will play a key role in driving subsystem timing closure, developing timing methodologies, and collaborating across engineering teams to deliver high-quality FPGA products.
Key Responsibilities:
  • Drive timing closure at block level and sub-system level.
  • Developing methodology through flow/scripting which will result in easier interface timing closure at full chip.
  • Define and manage I/O timing budgets across hierarchical designs.
  • Apply advanced sign-off methodologies at lower nodes, including POCV and PVT effects.
  • Provide actionable timing feedback at both block and sub-system levels, including root cause analysis and ECO guidance.
  • Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
  • Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
  • Global clock planning for easier interface timing closure.
  • Work closely with design, implementation, and full chip teams to drive timing convergence, providing sign-off level expertise and guidance.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$118,900 - $172,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Qualifications:
Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 5+ years of experience in ASIC or FPGA timing analysis and sign-off.
  • 5+ years of experience in timing analysis, static timing analysis (STA), and timing sign-off.
  • 5+ years of experience with timing constraints, STA methodologies, and timing closure at both the block and full-chip levels.
  • 5+ years of experience with synthesis, place-and-route, and parasitic extraction flows.
  • 5+ years of experience applying advanced timing concepts for leading-edge semiconductor technologies (5nm or below), including OCV, POCV, and PVT analysis.
  • 5+ years of experience performing multi-corner, multi-mode (MCMM) timing analysis.
  • 5+ years of experience using industry-standard timing analysis tools such as Cadence Tempus and Synopsys PrimeTime.
  • 5+ years of experience developing automation and scripting solutions using Tcl, Python, and/or Perl.
  • 5+ years of experience collaborating with RTL Design, Architecture, Physical Design, and Full Chip teams to drive timing closure.
  • Demonstrated ability to work independently with strong prioritization, problem-solving, and solution-oriented decision-making skills.

Preferred Qualifications
  • Experience with advanced FPGA or high-performance ASIC designs.
  • Experience developing timing methodologies and automation for large-scale hierarchical designs.
  • Experience defining hierarchical timing budgets and driving interface timing closure.
  • Experience generating and validating timing ECOs during implementation and sign-off.
  • Familiarity with clock tree synthesis (CTS), clock planning, and clock architecture optimization.
  • Strong understanding of digital design fundamentals and physical implementation methodologies.
  • Excellent analytical, debugging, and root cause analysis skills.
  • Strong written and verbal communication skills with the ability to collaborate across multidisciplinary engineering teams.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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