Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. * 4 years of technical experience in silicon timing closure and chip integration. * Experience in ...
Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. * 4 years of technical experience in silicon timing closure and chip integration. * Experience in ...
As TPM for Chip Tools, you'll shape how this space operates - driving dependency management, tool ... What We Need to See: * BS or MS in Electrical Engineering, Computer Engineering, Computer Science ...
PE CAD Engineering
$126.50K - $234.90K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the ...
PE CAD Engineering
$126.50K - $234.90K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the ...
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
... chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional ... Temporary Employees & Interns excluded
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
... chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional ... Temporary Employees & Interns excluded
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
Description As a Full Chip Integration Engineer, you will be participating in the physical design ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
CAD Designer Drafter
Houston, TX · On-site
As NASA's largest engineering solutions provider working together with NASA at centers across the United States. We have an exciting opportunity for a temporary CAD Designer Drafter to join the team.
CAD Designer Drafter
Houston, TX · On-site
As NASA's largest engineering solutions provider working together with NASA at centers across the United States. We have an exciting opportunity for a temporary CAD Designer Drafter to join the team.
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
As a Full Chip Integration Engineer, you will be participating in the physical design, integration ... CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with ...
CAD Engineer - Signoff Infrastructure
$147.40K - $272.10K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$147.40K - $272.10K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$147.40K - $272.10K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$147.40K - $272.10K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip ... Solid understanding of algorithms, computer architecture and computer science theory * Experienced ...
PE CAD Engineering
San Jose, CA · On-site
$126.50K - $234.90K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the ...
PE CAD Engineering
San Jose, CA · On-site
$126.50K - $234.90K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$113.51K - $190.90K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$113.51K - $190.90K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
PE CAD Engineering
$126.50K - $234.90K/yr
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the brightest ...
PE CAD Engineering
$126.50K - $234.90K/yr
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the brightest ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
CAD Engineer - PDV
$147.40K - $272.10K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...
Temporary Computer Chip Engineer information
See salary details
$48.5K - $56.6K
0% of jobs
$56.6K - $64.7K
0% of jobs
$64.7K - $72.8K
7% of jobs
$72.8K - $80.9K
0% of jobs
$80.9K - $89K
0% of jobs
$89K - $97K
1% of jobs
$97K - $105.1K
0% of jobs
$109.9K is the 25th percentile. Wages below this are outliers.
$105.1K - $113.2K
28% of jobs
$113.2K - $121.3K
1% of jobs
$121.3K - $129.4K
0% of jobs
The median wage is $131K / yr.
$129.4K - $137.5K
62% of jobs
$48.5K
$121.5K
$137.5K
How much do temporary computer chip engineer jobs pay per year?
As of Jun 1, 2026, the average yearly pay for temporary computer chip engineer in the United States is $121,515.00, according to ZipRecruiter salary data. Most workers in this role earn between $111,500.00 and $131,500.00 per year, depending on experience, location, and employer.
What cities are hiring for Temporary Computer Chip Engineer jobs? Cities with the most Temporary Computer Chip Engineer job openings:
What are the most commonly searched types of Computer Chip Engineer jobs? The most popular types of Computer Chip Engineer jobs are:
What states have the most Temporary Computer Chip Engineer jobs? States with the most job openings for Temporary Computer Chip Engineer jobs include:
Full-time
Posted 5 days ago
Google rating
8.8
Based on 92 frontline employees who took The Breakroom Quiz
30th of 184 rated software companies
Job description
Minimum qualifications:
Preferred qualifications:
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 4 years of technical experience in silicon timing closure and chip integration.
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
- Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
- Experience delivering silicon.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Science.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Experience with ASIC design flows and methodology of static timing analysis.
- Delivery of high-complexity silicon in state-of-the-art technology process nodes.
- Knowledge of semiconductor device physics and transistor characteristics.
- Effective skills with scripting languages such as Tcl or Perl.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Deliver system-on-chip (SoC) Static Timing Analysis.
- Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
- Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
- Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US