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Temporary Computer Chip Engineer Jobs (NOW HIRING)

Apple

CAD Engineer - PDV

Austin, TX · On-site

... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... As a member of our CAD team, you will architect, develop, maintain and improve physical design ...

Nova Ltd.

Mechanical Engineer

Fremont, CA · On-site

$110K - $130K/yr

Description We are seeking a Mechanical Design Engineer to join our multi-disciplinary team focused ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

Amentum

CAD Designer Drafter

Houston, TX · On-site

As NASA's largest engineering solutions provider working together with NASA at centers across the United States. We have an exciting opportunity for a temporary CAD Designer Drafter to join the team ...

Amentum

CAD Designer Drafter

Houston, TX · On-site

As NASA's largest engineering solutions provider working together with NASA at centers across the United States. We have an exciting opportunity for a temporary CAD Designer Drafter to join the team.

Apple

CAD Engineer - Signoff Infrastructure

Austin, TX · On-site

We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...

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How much do temporary computer chip engineer jobs pay per year?

As of Jun 22, 2026, the average yearly pay for temporary computer chip engineer in the United States is $121,515.00, according to ZipRecruiter salary data. Most workers in this role earn between $111,500.00 and $131,500.00 per year, depending on experience, location, and employer.
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Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

Austin, TX • On-site

$134K/yr

Other

Posted 20 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

13th of 60 rated aerospace companies

Job description

SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
  • Develop, maintain, and optimize physical verification flows for advanced node SoC's.
  • Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
  • Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
  • Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
  • Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

  • Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
  • Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
  • Deep expertise in DRC, LVS, PERC and ESD verification methodologies
  • Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
  • Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
  • Experience at advanced nodes (4nm and below)
  • Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
  • Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical project milestones    

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