Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. * Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming ...
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. * Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming ...
Design and develop ASIC, FPGA, and SoC-based microelectronic systems * Perform simulation ... Collaborative, engineering-driven environment * Strong potential for long-term growth and technical ...
Design and develop ASIC, FPGA, and SoC-based microelectronic systems * Perform simulation ... Collaborative, engineering-driven environment * Strong potential for long-term growth and technical ...
Circuit Design Engineer
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Annapolis, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Annapolis, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Catonsville, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
Catonsville, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
Circuit Design Engineer
$99K - $225K/yr
Experience with Register Transfer Level (RTL) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays (FPGAs) * TS/SCI clearance ...
That includes experience with ASIC design tools such as Cadence or Synopsis or FPGA design tools ... reverse engineering of the same. A bachelor's degree in a related field. Five (5) years of ...
That includes experience with ASIC design tools such as Cadence or Synopsis or FPGA design tools ... reverse engineering of the same. A bachelor's degree in a related field. Five (5) years of ...
Programmable Logic Design Engineer
Germantown, MD · On-site
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to ... Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field * 5-8 years ...
Programmable Logic Design Engineer
Germantown, MD · On-site
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to ... Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field * 5-8 years ...
They will design, document, and develop code (to include firmware) for digital signal processors or other programmable hardware devices such as Application Specific Integrated Circuit (ASIC) and ...
They will design, document, and develop code (to include firmware) for digital signal processors or other programmable hardware devices such as Application Specific Integrated Circuit (ASIC) and ...
Markesman Group is seeking Hardware Design Engineer (HDE) candidates to join our team. The HDE ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
Markesman Group is seeking Hardware Design Engineer (HDE) candidates to join our team. The HDE ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
FPGA Hardware Design Engineer
Hanover, MD · On-site
$122K - $168K/yr
Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ... Direct and check the work of other hardware design engineers * Act as internal consultant providing ...
FPGA Hardware Design Engineer
Hanover, MD · On-site
$122K - $168K/yr
Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ... Direct and check the work of other hardware design engineers * Act as internal consultant providing ...
The Hardware Design Engineer (HDE) designs and tests new integrated circuits and hardware ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
The Hardware Design Engineer (HDE) designs and tests new integrated circuits and hardware ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
FPGA Hardware Design Engineer
Hanover, MD · On-site
Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ... Direct and check the work of other hardware design engineers * Act as internal consultant providing ...
FPGA Hardware Design Engineer
Hanover, MD · On-site
Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ... Direct and check the work of other hardware design engineers * Act as internal consultant providing ...
FPGA Verification Engineer with Security Clearance
Arlington, VA · On-site
$141K - $195K/yr
... Debug RTL failures in simulation and on hardware targets • Develop constrained-random and ... with design engineers on architecture reviews and interface specifications • Support hardware ...
FPGA Verification Engineer with Security Clearance
Arlington, VA · On-site
$141K - $195K/yr
... Debug RTL failures in simulation and on hardware targets • Develop constrained-random and ... with design engineers on architecture reviews and interface specifications • Support hardware ...
Circuit Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level ( RTL ) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays ( FPGAs ) * TS/SCI ...
Circuit Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$99K - $225K/yr
Experience with Register Transfer Level ( RTL ) in circuit design, including RTL design, verification, and timing analysis * Experience with Field Programmable Gate Arrays ( FPGAs ) * TS/SCI ...
This role is ideal for an engineer who thrives in a hands-on environment, working across the full ... Design and develop ASIC, FPGA, and SoC-based microelectronic systems Perform simulation ...
This role is ideal for an engineer who thrives in a hands-on environment, working across the full ... Design and develop ASIC, FPGA, and SoC-based microelectronic systems Perform simulation ...
Hardware Design Engineer, Level 3 (2026-0068) with Security Clearance
Annapolis Junction, MD · On-site
$212K - $258K/yr
FPGA/ASIC knowledge required. Will be responsible for investigating COTS software protocols ... Five years of additional hardware design engineering experience may be substituted for a bachelor ...
Hardware Design Engineer, Level 3 (2026-0068) with Security Clearance
Annapolis Junction, MD · On-site
$212K - $258K/yr
FPGA/ASIC knowledge required. Will be responsible for investigating COTS software protocols ... Five years of additional hardware design engineering experience may be substituted for a bachelor ...
Title Hardware Design Engineer Level 1-3 Location Fort Meade Description Markesman Group is seeking ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
Title Hardware Design Engineer Level 1-3 Location Fort Meade Description Markesman Group is seeking ... Apply ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
... design or reverse engineering with a Bachelor of Science in Electrical Engineering or Computer ... Applying ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
Quick apply
... design or reverse engineering with a Bachelor of Science in Electrical Engineering or Computer ... Applying ASIC or FPGA place and route (P&R) tools with various libraries to create physical ...
Hardware Design Engineer, Level 3 (2026-0068)
Annapolis, MD · On-site
$212K - $258K/yr
FPGA/ASIC knowledge required. Will be responsible for investigating COTS software protocols ... Five years of additional hardware design engineering experience may be substituted for a bachelor ...
Hardware Design Engineer, Level 3 (2026-0068)
Annapolis, MD · On-site
$212K - $258K/yr
FPGA/ASIC knowledge required. Will be responsible for investigating COTS software protocols ... Five years of additional hardware design engineering experience may be substituted for a bachelor ...
Temporary Asic Rtl Design Engineer information
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
Full-time
Medical, Life, Retirement
Posted 7 days ago
Boeing rating
8.5
Based on 594 frontline employees who took The Breakroom Quiz
34th of 519 rated manufacturers
Job description
Company:
Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Verification Engineers (Experienced, Lead, or Senior) to join us as part of our Boeing Electronic Products team in either El Segundo or Huntington Beach, CA. An alternative location that may become available based on program needs could be Fairfax, VA.
From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes, the Boeing Electronic Products group develops ASICs and FPGAs that are at the heart of Boeing's products!
We leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. We apply the latest digital IC design processes with industry-best tools to enable applications which cut across every domain at Boeing.
Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line - approximately half our design/verification work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).
As an ASIC/FPGA Verification Engineer on the Boeing Electronic Products team you will verify state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise. We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics which we build in El Segundo or various other Boeing sites.
Position Responsibilities:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed location options.
This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Basic Qualifications (Required Skills/Experience):
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
5+ years of proven experience in ASIC/FPGA verification processes
Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Demonstrated experience in implementing test plans effectively
Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
Capability to design self-checking and reusable testbenches from the ground up
Experience in developing Functional Coverage Models and achieving Code Coverage closure
Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
Familiarity with waveform debug tools
Revision Control Systems: svn, cvs, git
Proficiency in Linux Environments
Preferred Qualifications (Desired Skills/Experience):
Lead, Level 4: 10+ years of related work experience or an equivalent combination of education and experience
Senior, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
Experience with hardware-based integration and test of ASIC/FPGA designs
Experience with hardware emulators, especially Palladium
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
Proficient in scripting languages: Make, Perl, Python, etc.
Familiarity with space-based design techniques and radiation mitigation
Demonstrated history of 1st pass success with ASIC designs
Conflict of Interest:
Successful candidate for this job must satisfy the Company's Conflict of Interest (COI) assessment process.
Typical Education/Experience:
Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Senior, Level 5:
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Relocation:
This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.
Drug Free Workplace:
Boeingis a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Shift Work Statement:
This position is for 1st shift.
At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.
The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.
The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.
Pay is based upon candidate experience and qualifications, as well as market and business considerations.
Summary pay range for Experienced (Level 3) $119,850 - $162,150
Summary pay range for Lead (Level 4): $126,650 - $171.350 $146,200 - $197,800
Summary pay range for Senior (Level 5) : $176,800 - $239,200
Language Requirements:
Not ApplicableEducation:
Bachelor's Degree or EquivalentRelocation:
This position offers relocation based on candidate eligibility.Export Control Requirement:
Safety Sensitive:
Security Clearance:
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.Visa Sponsorship:
Employer will not sponsor applicants for employment visa status.Contingent Upon Award Program
This position is not contingent upon program awardShift:
Shift 1 (United States of America)Stay safe from recruitment fraud! The only way to apply for a position at Boeing is via our Careers website. Learn how to protect yourself from recruitment fraud - Recruitment Fraud Warning
Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.
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