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Temporary Asic Rtl Design Engineer Jobs in Rhode Island

Sr Hydraulic Engineer

Cranston, RI · Hybrid

$102K - $140K/yr

... Design for Manufacturing (DFM) and Statistical Process Control (SPC) to identify quality and reliability issues. * Creates and manages engineering change orders (ECO) and temporary change notices ...

Senior Traffic Engineer

Lincoln, RI · On-site

$106K - $160K/yr

... and temporary traffic controls * Manage traffic related projects * Technical design lead on ... Professional Engineer (PE) License * Demonstrated strong background in traffic and transportation ...

Senior Traffic Engineer

Lincoln, RI · On-site

$106K - $160K/yr

... and temporary traffic controls * Manage traffic related projects * Technical design lead on ... Professional Engineer (PE) License * Demonstrated strong background in traffic and transportation ...

Senior Traffic Engineer

Lincoln, RI · Hybrid

$106K - $160K/yr

... and temporary traffic controls * Manage traffic related projects * Technical design lead on ... Professional Engineer (PE) License * Demonstrated strong background in traffic and transportation ...

Sr Hydraulic Engineer

Cranston, RI · On-site

$102K - $140K/yr

... Design for Manufacturing (DFM) and Statistical Process Control (SPC) to identify quality and reliability issues. * Creates and manages engineering change orders (ECO) and temporary change notices ...

In these positions, candidates will provide system design,integration and test, and operational ... Identifying temporary workarounds for problems while long term solutions are analyzed.

This is a full-time temporary assignment not to exceed 1 year. May be filled as a temporary ... and reviewing engineering design for proposed changes. Reviewing contractor cost proposals to ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Job description

Job Summary: SEACORP has immediate full-time openings for recentlyseparated submarine officers who will provide support as Systems Engineers inNewport, RI. In these positions, candidates will provide system design,integration and test, and operational support for 3rd Party Targeting, BYG-1Combat Control System, Common Submarine Radio Room and the Tomahawk WeaponSystem on all submarine classes. The primary office location is located inNewport, Rhode Island supporting labs at NUWC Newport but may include travel tosupport events onboard submarines both dockside and underway, and at shoresites at different theatres. 

Core Responsibilities:

  • Working with customer program leads to review system designs and provide recommendations for implementation based on operational experience.
  • Identifying, investigating and analyzing software and hardware failures to determine root-causes.
  • Providing lab test support evaluating new system capabilities and troubleshooting problems.
  • Identifying temporary workarounds for problems while long term solutions are analyzed.
  • Identifying operational risks associated with all reported failures.
  • Writing clear and concise problem reports.
  • Attendingmeetings as applicable and provide necessary verbal communication.