About OLIX
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
The Role
We are seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design to take end-to-end ownership of high-speed, real-time data-processing silicon, from early algorithm modelling to verified RTL and silicon bring-up. You will join a multidisciplinary group creating next-generation hardware where digital, optical and mixed-signal domains intersect. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware.
Responsibilities
- Architect, design and implement highโthroughput digital pipelines (multiโGSPS input rate, continuous streaming data paths, deep pipelining and handโshaking) in advanced CMOS nodes
- Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bringโup realโtime demos, exercise highโspeed transceivers, and feed learnings back into the ASIC
- Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gateโlevel signโoff
- Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, staticโtiming closure, formal and constrainedโrandom verification
- Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidthโperโwatt targets
- Collaborate with opticalโhardware, mixedโsignal and software teams to optimise dataโconverter interfaces, clockโdomain crossings and firmware abstractions
- Mentor junior engineers, lead design reviews and champion bestโpractice design methodologies
Skills & Experience
- 7+ years of handsโon digital design for highโperformance ASICs or SoCs, including ownership of at least one product that processes a continuous realโtime data stream
- Proven success closing timing on multiโhundredโMHz to multiโGHz clock domains and integrating highโspeed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)
- Expertise with industryโstandard EDA flows: RTL synthesis, CDC/RDC, STA, powerโintent (UPF/CPF), lint, and gateโlevel simulation
- Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab
- Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixedโpoint analysis and testโvector generation
- Solid grounding in digital signalโprocessing concepts, computerโarchitecture fundamentals and semiconductor device physics
- Excellent communication and crossโfunctional collaboration abilities; thrives in a fastโmoving, ambiguous environment
Nice to have
- Tapeโout experience at 22 nm or below
- Knowledge of coherent optical links or photonicโelectronic coโdesign.
- Familiarity with AI/ML workloads, systolic arrays or tensorโprocessing architectures.
- Contributions to openโsource RTL, verification frameworks or FPGA boards.
Compensation & Equity
- Competitive Salary: Commensurate with your experience, skills, and location
- Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it
- Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
- Retirement Benefits:Employer-contributed retirement plans to help you build long-term financial security
Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.