ZipRecruiter

Log In

1

Synopsys Verification Engineer Jobs (NOW HIRING)

Voltai, Inc

Formal Verification Engineer

Palo Alto, CA · On-site

$159K/yr

... Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense ... You'll collaborate closely with RTL, verification, and ML research teams to develop hybrid formal ...

Intel

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

Who You Are Join Intel's Silicon Engineering Group as a CPU Design Verification Engineer, where you ... Experience using industry-standard simulation tools like Synopsys VCS and version control systems ...

Intel

CPU Verification Engineer

Hillsboro, OR · On-site

$148K/yr

Who You Are Join Intel's Silicon Engineering Group as a CPU Design Verification Engineer, where you ... Experience using industry-standard simulation tools like Synopsys VCS and version control systems ...

Voltai

Formal Verification Engineer

Palo Alto, CA · On-site

$159K/yr

... Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense ... You'll collaborate closely with RTL, verification, and ML research teams to develop hybrid formal ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

Who You Are Join Intel's Silicon Engineering Group as a CPU Design Verification Engineer, where you ... Experience using industry-standard simulation tools like Synopsys VCS and version control systems ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$105K - $200K/yr

Who You Are We are seeking a highly motivated CPU verification engineer to join our design team. In ... Experience with Synopsys simulators. * Experience with agile development methodologies. * Excellent ...

Intel

CPU Verification Engineer

Austin, TX · On-site

$105K - $200K/yr

Who You Are We are seeking a highly motivated CPU verification engineer to join our design team. In ... Experience with Synopsys simulators. * Experience with agile development methodologies. * Excellent ...

Voltai, Inc

Formal Verification Engineer

Palo Alto, CA · Hybrid

$160K/yr

... Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense ... You'll collaborate closely with RTL, verification, and ML research teams to develop hybrid formal ...

Intel

CPU Verification Engineer

Hillsboro, OR · On-site

$105K - $200K/yr

Who You Are We are seeking a highly motivated CPU verification engineer to join our design team. In ... Experience with Synopsys simulators. * Experience with agile development methodologies. * Excellent ...

Intel

CPU Verification Engineer

Austin, TX · On-site

$105K - $200K/yr

Join Intel's Silicon Engineering Group as a CPU Design Verification Engineer, where you will play a ... Experience with Synopsys simulators (e.g., VCS), debug tools, and version control software such as ...

TeamGlobal

FPGA Design/Verification Engineer

Littleton, CO · Hybrid

$89.13 - $110/hr

FPGA Design/Verification Engineer Location: Littleton, CO Salary Range: 89.13 Position: FPGA ... Experience with Libero, Vivado, and Synopsys Tools (Simulation, Lint/CDC, and Synthesis) * Design ...

Futran Tech Solutions Pvt. Ltd.

DV Engineer

Dallas, TX · On-site

$125K - $153K/yr

Looking for a senior verification engineers to manage complex subsystem verification with Synopsys peripherals Hands on experience on testbench development, test plan, coverage and validation for new ...

next page

Showing results 1-20

People also search for

All JobsSynopsys Verification Engineer Jobs

Synopsys Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do synopsys verification engineer jobs pay per year?

As of Jun 6, 2026, the average yearly pay for synopsys verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Synopsys Verification Engineer, and why are they important?

To thrive as a Synopsys Verification Engineer, you need a solid background in digital design, hardware description languages (like Verilog or VHDL), and verification methodologies, often supported by a degree in electrical or computer engineering. Familiarity with Synopsys verification tools (such as VCS, Verdi, or Design Compiler), scripting languages (Perl, Python, TCL), and UVM methodology is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help engineers excel in identifying design flaws and collaborating with design teams. These competencies are crucial for ensuring chip designs are robust, functional, and delivered on schedule in highly complex semiconductor projects.

What does a Synopsys Verification Engineer do?

A Synopsys Verification Engineer specializes in verifying the functionality and performance of integrated circuits and systems using Synopsys tools and methodologies. They develop and execute test plans, create testbenches, and utilize hardware description languages (HDLs) like Verilog or VHDL to ensure designs meet specifications. These engineers work closely with design teams to identify and resolve issues early in the development process, often using simulation, formal verification, and emulation technologies. Their work is essential for delivering high-quality, reliable semiconductor products.

What is the difference between Synopsys Verification Engineer vs FPGA Verification Engineer?

AspectSynopsys Verification EngineerFPGA Verification Engineer
CredentialsBachelor's/Master's in Electrical Engineering, Computer Engineering, or related fields; knowledge of verification toolsBachelor's/Master's in Electrical Engineering, Computer Engineering, or related fields; experience with FPGA design and verification tools
Work EnvironmentSemiconductor and EDA tool companies, design teams, verification labsHardware design firms, FPGA development teams, embedded systems companies
Industry UsageUsed in semiconductor, ASIC, and verification tool industriesCommon in digital hardware, embedded systems, and FPGA development sectors

The Synopsys Verification Engineer focuses on verifying integrated circuit designs using Synopsys tools, while the FPGA Verification Engineer specializes in testing FPGA hardware designs. Both roles require strong verification skills, but the former emphasizes software-based verification in chip design, whereas the latter concentrates on hardware testing and FPGA development.

How does a Synopsys Verification Engineer typically collaborate with design and software teams during a project?

As a Synopsys Verification Engineer, collaboration with both design and software teams is a fundamental part of the workflow. You will regularly interact with design engineers to review specifications, clarify functional requirements, and debug issues identified during simulation or emulation. Additionally, you may work closely with software teams to ensure that verification environments are compatible with firmware or drivers and to validate end-to-end functionality. Frequent communication and joint problem-solving sessions are essential to ensure that verification goals align with overall project milestones.
Infographic showing various Synopsys Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 25% Part Time, and 75% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.
Mixed-signal Design Verification Engineer

Mixed-signal Design Verification Engineer

Pacer Group

Santa Clarita, CA • On-site

$138K - $168K/yr

Contractor

Posted 23 days ago

Job description

Job Title: Mixed-signal Design Verification Engineer
Job Location: Santa Clara, CA
Job Duration: 3 Months, Contract to Hire
 
Qualifications:
  • 7+ years of experience in pre-silicon design verification
  • Proficiency in C-shell scripting, Verilog-HDL & System Verilog.
  • Strong knowledge in SV Assertions, UVM/OVM and functional code coverage.
  • SOC Verification experience using ARM Cortex Microcontroller is required.
  • Experience with advanced peripheral bus Verification IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C.
  • Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
  • Exposure to FPGA programming and FPGA tools will be helpful.
  • Independent, self-motivated with good analytical & communication skills."
Job Responsibilities:
  • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
  • Running complete set of design verification tools available on AMS blocks
  • Execute multiple projects with emphasis on AMS and Power aware verification.
  • Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
  • Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
  • Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
  • Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
  • Work with architects to determine the use-case scenarios to simulate"
Mandatory Skills:
  • Synopsys/Cadence EDA/DV tools (Preference: 5)
  • AMS tools and Simulations (Preference: 5)
  • SystemVerilog/UVM (Preference: 5)
  • Python (Preference: 3)