ASIC RTL/SoC Design Engineer
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
$159K - $194K/yr
Experience in SoC verification cycle from architecture to tape out to bring up. * Good knowledge of verification methodologies such as UVM/OVM etc. * Hand on ASIC-SoC Design verification tests and ...
$159K - $194K/yr
Experience in SoC verification cycle from architecture to tape out to bring up. * Good knowledge of verification methodologies such as UVM/OVM etc. * Hand on ASIC-SoC Design verification tests and ...
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
Quick apply
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
$115K - $135K/yr
Position SummaryAs a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations ...
$115K - $135K/yr
Position SummaryAs a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations ...
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred ...
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
$94K - $103.8K
16% of jobs
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$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
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$162.7K - $172.5K
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$94K
$150.2K
$202K
Full-time
Medical, Retirement, PTO
Re-posted 11 days ago
TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.
We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.
Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.
Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.
Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.
Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.
Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.
Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.
Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.
Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.
MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
Experience with Verilog and system Verilog
Experience with VCS, Verdi or other industry standard tools
Experience with pre-layout simulation and post-layout simulation
Understanding of the design flow. Ability to work with the backend team
Familiarity with AMBA APB AXI Protocol
Familiarity with RISC/Arm or other core architectures
Ability to create innovative architecture and solutions to customer requirements
Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a strong plus:
FPGA/ASIC design of image processing systems
Working knowledge of SoC architecture such as CPU, GPU or accelerators
Familiarity with: UVM, place-and-route, STA, EM/IR/Power
All your information will be kept confidential according to EEO guidelines.
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Computer and peripheral equipment manufacturing
11 - 50 Employees
Fremont, CA, US
2018