Job Details:**## The Advanced Packaging Technology Development (APTD) Substrate and Wafer Assembly ... Responsibilities** • Collaborate with suppliers and internal engineering teams to develop robust ...
Job Details:**## The Advanced Packaging Technology Development (APTD) Substrate and Wafer Assembly ... Responsibilities** • Collaborate with suppliers and internal engineering teams to develop robust ...
Electromechanical Engineer
San Francisco, CA · On-site
$150K - $275K/yr
Electromechanical Engineer Substrate is addressing one of the most important technological problems ... Summary In this role, you will lead the development of next-generation high-precision electrostatic ...
Electromechanical Engineer
San Francisco, CA · On-site
$150K - $275K/yr
Electromechanical Engineer Substrate is addressing one of the most important technological problems ... Summary In this role, you will lead the development of next-generation high-precision electrostatic ...
Packaging Substrate Engineer
$184K - $324K/yr
Description • Lead SoC package substrate technology development, pathfinding, and roadmap ... Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of ...
Packaging Substrate Engineer
$184K - $324K/yr
Description • Lead SoC package substrate technology development, pathfinding, and roadmap ... Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of ...
Packaging Substrate Engineer
$184K - $324K/yr
Description • Lead SoC package substrate technology development, pathfinding, and roadmap ... Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of ...
Packaging Substrate Engineer
$184K - $324K/yr
Description • Lead SoC package substrate technology development, pathfinding, and roadmap ... Proven fundamentals in material/chemistry/mechanical engineering field(s). In-depth knowledge of ...
Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
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Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
Process Engineer Substrate is addressing one of the most important technological problems facing ... You will be a key contributor to early-stage development and testing which are critical to our ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
Process Engineer Substrate is addressing one of the most important technological problems facing ... You will be a key contributor to early-stage development and testing which are critical to our ...
Substrate Quality and Reliability Engineer
$101K - $128K/yr
As a Substrate Quality and Reliability Engineer you will drive substrate capacity expansion to ... development activities at a component level and address product manufacturing challenges at ...
New
Substrate Quality and Reliability Engineer
$101K - $128K/yr
As a Substrate Quality and Reliability Engineer you will drive substrate capacity expansion to ... development activities at a component level and address product manufacturing challenges at ...
New
Electromechanical Engineer
San Francisco, CA · On-site
$150K - $275K/yr
At the intersection of advanced manufacturing and cutting-edge physics, Substrate is developing ... Summary In this role, you will lead the development of next-generation high-precision electrostatic ...
Electromechanical Engineer
San Francisco, CA · On-site
$150K - $275K/yr
At the intersection of advanced manufacturing and cutting-edge physics, Substrate is developing ... Summary In this role, you will lead the development of next-generation high-precision electrostatic ...
Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
Substrate IC Package Layout Design Engineer
San Jose, CA · On-site
$2.0K/mo
Lead the design and development of complex IC substrate layouts for high-power AI processors and ... Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
Packaging Substrate Engineer
San Francisco, CA · On-site
$129K - $225K/yr
Description Lead SoC package substrate technology development, pathfinding, and roadmap definition. Work with substrate manufacturing industry, foundry, and OSAT to bring package substrate solution ...
Packaging Substrate Engineer
San Francisco, CA · On-site
$129K - $225K/yr
Description Lead SoC package substrate technology development, pathfinding, and roadmap definition. Work with substrate manufacturing industry, foundry, and OSAT to bring package substrate solution ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
Senior Process Engineer
San Francisco, CA · On-site
$200K - $300K/yr
Senior Process Engineer Substrate is addressing one of the most important technological problems ... You will be a key contributor to early-stage development and testing which are critical to our ...
Senior Process Engineer
San Francisco, CA · On-site
$200K - $300K/yr
Senior Process Engineer Substrate is addressing one of the most important technological problems ... You will be a key contributor to early-stage development and testing which are critical to our ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
Substrate/Package Layout Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom OSD is looking for an IC Substrate and Package/Interposer Layout Engineer. In the role ... Contribute to the development and improvement of layout methodologies and flows Job requirements:
Substrate/Package Layout Engineer
San Jose, CA · On-site
$141K - $226K/yr
Broadcom OSD is looking for an IC Substrate and Package/Interposer Layout Engineer. In the role ... Contribute to the development and improvement of layout methodologies and flows Job requirements:
This role is critical in shaping the direction of 3DIC development. Overview We are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting-edge 3DIC design ...
This role is critical in shaping the direction of 3DIC development. Overview We are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting-edge 3DIC design ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
At the intersection of advanced manufacturing and cutting-edge physics, Substrate is developing ... You will be a key contributor to early-stage development and testing which are critical to our ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
At the intersection of advanced manufacturing and cutting-edge physics, Substrate is developing ... You will be a key contributor to early-stage development and testing which are critical to our ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI ... Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM ...
Substrate Development Engineer information
See salary details
$24.28 - $26.20
3% of jobs
$28.10 is the 25th percentile. Wages below this are outliers.
$26.20 - $28.13
22% of jobs
The median wage is $29.28 / hr.
$28.13 - $30.05
41% of jobs
$31.18 is the 75th percentile. Wages above this are outliers.
$30.05 - $31.97
15% of jobs
$31.97 - $33.89
16% of jobs
$33.89 - $35.82
0% of jobs
$35.82 - $37.74
0% of jobs
$37.74 - $39.66
0% of jobs
$39.66 - $41.59
0% of jobs
$41.59 - $43.51
0% of jobs
$43.51 - $45.43
3% of jobs
$24
$30
$45
How much do substrate development engineer jobs pay per hour?
What is the difference between Substrate Development Engineer vs Blockchain Developer?
| Aspect | Substrate Development Engineer | Blockchain Developer |
|---|---|---|
| Credentials | Knowledge of Rust, blockchain architecture, and Substrate framework | Proficiency in blockchain languages like Solidity, JavaScript, or Python |
| Work Environment | Focus on blockchain infrastructure, protocol development, and substrate-based chains | Developing decentralized applications, smart contracts, and blockchain solutions |
| Industry Usage | Primarily in blockchain infrastructure companies and projects using Substrate | In various blockchain projects, DApps, and smart contract platforms |
While both roles involve blockchain technology, a Substrate Development Engineer specializes in building blockchain frameworks using the Substrate platform, whereas a Blockchain Developer focuses on creating applications and smart contracts on various blockchain platforms.
What are popular job titles related to Substrate Development Engineer jobs?
For Substrate Development Engineer jobs, the most frequently searched job titles are:

Substrate Supplier Enablement Engineer
Phoenix, AZ • On-site
Other
Medical, Retirement, PTO
Re-posted 8 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
Job description
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968