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Substrate Design Engineer Ic Packaging Jobs (NOW HIRING)

Lightmatter

Package Layout Engineer

Mountain View, CA · Hybrid

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Educational background in IC packaging and substrate layout design. * Familiarity with system-level ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

Leverage advanced packaging technologies, with expertise in CoWoS (Chip-on-Wafer-on-Substrate) and heterogeneous integration techniques, to design both open and closed packages, incorporating ...

Apple

IC Package Design Engineer

Los Angeles, CA · On-site

$146K/yr

Our Packaging team defines, designs, and integrates advanced electronic packaging solutions for ... Solid grasp of substrate manufacturing processes, design rules (DRC), design for manufacturability ...

Apple

IC Package Design Engineer

Austin, TX · On-site

$134K/yr

Our Packaging team defines, designs, and integrates advanced electronic packaging solutions for ... Solid grasp of substrate manufacturing processes, design rules (DRC), design for manufacturability ...

Axiado

Senior IC Packaging Engineer

San Jose, CA · On-site

$122K - $168K/yr

Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and ... design trade-offs, Advanced packaging materials and substrate technologies, Design-for ...

Intel

Silicon Packaging Design Engineer

Phoenix, AZ

$105K - $149K/yr

As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of ... Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.

Micross

Package Design Engineer | Semiconductor

Apopka, FL · On-site

$119K/yr

... interposer / substrate stack up * Work with IC design team to define IC package requirements ... Bachelors degree in Electrical Engineering, Mechanical Engineering, or other semiconductor ...

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Substrate Design Engineer Ic Packaging information

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$90K

$136.5K

How much do substrate design engineer ic packaging jobs pay per year?

As of Sep 10, 2026, the average yearly pay for substrate design engineer ic packaging in the United States is $135,040.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a substrate design engineer in IC packaging?

A Substrate Design Engineer in IC Packaging is a specialized engineer who focuses on designing the substrates that connect and support integrated circuits (ICs) within electronic packages. These substrates serve as the bridge between the silicon chip and the printed circuit board (PCB), providing electrical connections, mechanical support, and thermal management. The engineer works closely with cross-functional teams to optimize layout, materials, and manufacturing processes, ensuring high performance and reliability of electronic products. Their role is critical in enabling advanced semiconductor devices, such as processors and memory chips, to function efficiently in various applications.

What skills and qualifications are needed to thrive as a substrate design engineer in IC packaging?

To excel as a Substrate Design Engineer in IC Packaging, a solid background in electrical engineering, circuit design, and materials science—often with a relevant bachelor's or master's degree—is essential. Familiarity with EDA tools (such as Cadence Allegro or Mentor Graphics), PCB/IC packaging standards, and simulation software is typically required, alongside knowledge of industry certifications like IPC. Outstanding problem-solving, collaboration, and communication skills help engineers coordinate with cross-functional teams and address complex design challenges. These competencies ensure reliable, high-performance substrate solutions that meet manufacturing, cost, and quality requirements in advanced electronics.

How does a substrate design engineer in IC packaging typically collaborate with cross-functional teams during a project?

As a Substrate Design Engineer in IC Packaging, you'll work closely with electrical engineers, mechanical engineers, and manufacturing teams to ensure the substrate meets both electrical and physical requirements. Collaboration often involves regular design reviews, troubleshooting sessions, and iterative feedback to align on performance, cost, and manufacturability targets. Communication skills are vital, as you'll translate technical requirements between design and production, and may also interact with suppliers or customers to address specific needs or constraints. This cross-functional teamwork is essential for delivering reliable, high-performance IC packages on schedule.
Infographic showing various Substrate Design Engineer Ic Packaging job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $135,040 per year, or $64.9 per hour.

Package Layout Engineer

Mountain View, CA • Hybrid

Lightmatter
See more jobs at Lightmatterexternal

Full-time

Posted 20 days ago

Job description

About This Role

Lightmatter is looking for a Package Layout Design Engineer to drive the next generation products from concept to development. You will be part of the Signal Integrity, Power Integrity and Packaging team, tasked with delivering substrate layouts that support the package architecture from concept, through design optimization and completion, meeting stringent signal integrity, power integrity, and design for manufacturing requirements. This position offers a unique opportunity to work on new package architectures by solving complex interactions across digital, analog and photonics domains. 

Responsibilities
  • Deliver IC package substrate layouts for standard and advanced packaging technologies.
  • Contribute to the product concept phase by delivering preliminary substrate designs and floorplanning to support overall stack-up (Silicon/package/MB) optimization.
  • Collaborate with package substrate suppliers and Outsourced Semiconductor Assembly and Test (OSAT) companies to apply layout design rules, stack up, and implementation guidelines.
  • Generate fab files and coordinate with substrate suppliers and OSATs to support Design for Manufacturing (DFM) and Design for Assembly (DFA) closure.
  • Design package layouts while adhering to signal integrity, power integrity, thermal, and mechanical requirements.
  • Design packages incorporating analog and digital elements/interfaces.
  • Support signal/power integrity engineers by providing iterative test routes to refine design rules and routing topologies.
  • Coordinate across functional teams to execute error-free Package Design Tape Outs on schedule.
  • Support and adapt design automation and verification activities to improve team efficiency.
Qualifications
  • B.S. or M.S. degree in Electrical Engineering or similar discipline with at least 5 years of relevant experience
  • Minimum 3-5 years of experience in IC package layout design.
  • Proficient with Allegro X APD.
  • Understanding of IC package substrates and organic materials, and their impact on package design.
Preferred Qualifications
  • Educational background in IC packaging and substrate layout design.
  • Familiarity with system-level validation tools such as Cadence Integrity 3DIC for package/IC codesign.
  • Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout, Altium, etc.).
  • Experience with layout tool scripting languages (e.g., SKILL or Python) to enable design automation.
  • Exposure to or interest in early-stage architectural pathfinding and physical feasibility studies for multi-chiplet and advanced packaging architectures (2.5D/3D IC, Silicon Interposers, EMIB, Fan-Out Chip-on-Wafer, etc.).
  • Experience evaluating floorplans, escape routing, bump patterns (micro-bumps / hybrid bonding), and die-to-die (D2D) interface topologies.
  • Excellent communication skills and the ability to collaborate effectively in cross-functional teams.

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