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Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. We are looking for a Senior ASIC Design Verification Engineer (L3 or L4) to contribute to the verification of complex digital and mixed-signal ASIC, SoC, subsystem, IP, and FPGA designs. This role is ideal for an experienced verification engineer who enjoys building robust verification environments, developing high-quality tests and coverage models, debugging complex issues, and collaborating closely with cross-functional engineering teams.Job SummaryAs a Senior ASIC Design Verification Engineer, you will be responsible for developing and executing verification plans for complex ASIC, SoC, subsystem, IP, and FPGA designs. You will work with architects, RTL designers, analog/mixed-signal engineers, firmware developers, and other verification engineers to ensure designs meet functional, performance, and quality requirements.This is a hands-on technical role focused on verification environment development, test creation, coverage-driven verification, regression debug, and verification closure. You will contribute to reusable verification infrastructure and help improve verification efficiency across projects.Key Responsibilities• Develop and execute verification plans for ASIC, SoC, subsystem, IP, and FPGA designs.• Build and maintain verification environments using SystemVerilog, UVM, constrained-random testing, directed testing, and assertion-based verification.• Create and enhance testbench components, including agents, monitors, drivers, scoreboards, sequences, checkers, and coverage models.• Develop directed and constrained-random test cases to verify functional requirements and corner cases.• Analyze design specifications and collaborate with architects and RTL designers to identify verification requirements.• Drive verification closure using functional coverage, code coverage, assertion coverage, regression results, and bug tracking.• Debug RTL, testbench, and integration issues using simulation logs, waveforms, coverage data, and EDA debug tools.• Participate in design and verification reviews, providing technical feedback on specifications, test plans, coverage models, and verification results.• Support regression development, automation, and continuous improvement of verification flows.• Work closely with design, firmware, analog/mixed-signal, FPGA, and program teams to resolve issues and achieve project milestones.• Contribute to verification methodology improvements, reusable verification components, and project-level best practices.• Mentor junior engineers as appropriate through code reviews, debug support, and technical guidance.Qualifications• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.• Typically 5+ years of ASIC, SoC, FPGA, or IP design verification experience.• Strong hands-on experience with SystemVerilog and UVM.• Experience developing block-level, IP-level, subsystem-level, or SoC-level verification environments.• Experience creating verification plans, test cases, sequences, scoreboards, checkers, assertions, and functional coverage models.• Solid understanding of constrained-random verification, directed testing, regression management, and coverage-driven verification closure.• Strong debug skills for RTL, testbench, and integration issues.• Experience with scripting and automation using languages such as Python, Perl, Tcl, shell scripting, or Make.• Familiarity with industry-standard EDA tools for simulation, waveform debug, coverage analysis, or verification management.• Ability to read and interpret design specifications, microarchitecture documents, and protocol documentation.• Strong problem-solving skills and attention to detail.• Effective written and verbal communication skills.• Ability to collaborate effectively with architecture, design, verification, analog, firmware, FPGA, and program teams.Preferred Qualifications• Experience verifying complex SoCs, processors, accelerators, networking devices, high-performance datapaths, or AI/ML-oriented designs.• Experience with high-speed interfaces and protocols such as PCIe, CXL, DDR, LPDDR, Ethernet, USB, MIPI, AMBA, AXI, CHI, or UCIe.• Experience with formal verification, assertion-based verification, or property checking.• Experience with gate-level simulation, low-power verification, UPF/CPF, reset verification, or X-propagation analysis.• Experience with emulation, FPGA prototyping, hardware/software co-verification, or post-silicon bring-up support.• Familiarity with mixed-signal verification methodologies.• Experience working in customer-facing engineering environments or ASIC design services organizations.• Experience mentoring junior engineers or contributing to project-level methodology improvements.Why Join ForwardEdge ASIC?At ForwardEdge ASIC, you will work on challenging silicon programs with an experienced engineering team. You will contribute directly to the verification of advanced ASIC and FPGA designs, collaborate with talented engineers across disciplines, and help deliver high-quality custom silicon solutions for leading-edge applications.What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $130,000.00 - $170,000.00 Annually