Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
Summary The IC Packaging Design & Layout Engineer is responsible for the end to end creation of ... Experience with SI/PI analysis using Ansys SIwave and HFSS, Hyperlynx, or other industry standard ...
IC Packaging Design & Layout Engineer
Cambridge, MA · On-site
$82K - $220K/yr
Summary The IC Packaging Design & Layout Engineer is responsible for the end to end creation of ... Experience with SI/PI analysis using Ansys SIwave and HFSS, Hyperlynx, or other industry standard ...
Analog Layout Engineer
Austin, TX · On-site
$157K - $280K/yr
High Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly ... Cadence Innovus. CAD Automation experience. PCell creation experience. MSEE or Ph.D. in Electrical ...
Analog Layout Engineer
Austin, TX · On-site
$157K - $280K/yr
High Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly ... Cadence Innovus. CAD Automation experience. PCell creation experience. MSEE or Ph.D. in Electrical ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
Unlike typical VLSI roles, engineers here directly shape products that define the state of the art ... Drive the concepts of the transistor level standard cell circuit design, modeling and performance ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Sr. Engineer, Layout Design
Santa Clara, CA · On-site
$124K - $171K/yr
Job Summary The Senior Layout Design Engineer will lead top-chip, block-level and perform custom ... cell, and standard cell levels for CMOS and BiCMOS circuits * Execute schematic-driven layout ...
Quick apply
Sr. Engineer, Layout Design
Santa Clara, CA · On-site
$124K - $171K/yr
Job Summary The Senior Layout Design Engineer will lead top-chip, block-level and perform custom ... cell, and standard cell levels for CMOS and BiCMOS circuits * Execute schematic-driven layout ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive ...
Analog Layout Engineer
Austin, TX · On-site
$200K/yr
High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly ... Experience with Cadence Innovus, CAD Automation experience, PCell creation experience. Apple is an ...
Analog Layout Engineer
Austin, TX · On-site
$200K/yr
High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly ... Experience with Cadence Innovus, CAD Automation experience, PCell creation experience. Apple is an ...
The Opportunity We are seeking a versatile Analog Design and Layout Engineer to join a premier ... Mastery of industry-standard CAD environments (e.g., Cadence Virtuoso, SPICE simulators, or Mentor ...
The Opportunity We are seeking a versatile Analog Design and Layout Engineer to join a premier ... Mastery of industry-standard CAD environments (e.g., Cadence Virtuoso, SPICE simulators, or Mentor ...
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is ... Experience with analog DFM standards * Experience with layout P-cell design and implementation
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is ... Experience with analog DFM standards * Experience with layout P-cell design and implementation
We are now hiring for a Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a ...
We are now hiring for a Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a ...
Layout Engineer
San Antonio, TX · On-site
Title : Layout Engineer (LE): Auto CAD Location : San Antonio, Texas (Day 1 Onsite) Job Type ... Validate layout proposals to ensure feasibility and compliance with standards. * Optimize material ...
Quick apply
Layout Engineer
San Antonio, TX · On-site
Title : Layout Engineer (LE): Auto CAD Location : San Antonio, Texas (Day 1 Onsite) Job Type ... Validate layout proposals to ensure feasibility and compliance with standards. * Optimize material ...
JR2014331We are now hiring for a Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It ...
JR2014331We are now hiring for a Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It ...
... standards for future cell generations. Mask-set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
... standards for future cell generations. Mask-set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
... standards for future cell generations. Mask-set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
... standards for future cell generations. Mask-set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
... standards for future cell generations. Mask-Set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
... standards for future cell generations. Mask-Set & Pattern Design * Own mask-set design and layout ... Work closely with process engineers to ensure cell designs are compatible with sputtering ...
Standard Cell Design Layout Engineer information
See salary details
$45K - $57.8K
4% of jobs
$57.8K - $70.5K
2% of jobs
$70.5K - $83.3K
12% of jobs
$93.7K is the 25th percentile. Wages below this are outliers.
$83.3K - $96.1K
9% of jobs
$96.1K - $108.9K
11% of jobs
The median wage is $120.7K / yr.
$108.9K - $121.6K
14% of jobs
$121.6K - $134.4K
22% of jobs
$136.8K is the 75th percentile. Wages above this are outliers.
$134.4K - $147.2K
9% of jobs
$147.2K - $160K
9% of jobs
$160K - $172.7K
3% of jobs
$172.7K - $185.5K
6% of jobs
$45K
$120.8K
$185.5K
How much do standard cell design layout engineer jobs pay per year?
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For Standard Cell Design Layout Engineer jobs, the most frequently searched job titles are:

Circuit Design Engineer - Standard Cell
Santa Clara, CA • On-site
Full-time
Re-posted 5 days ago
Key responsibilities
Work on the design, modeling, and performance analysis of standard cell libraries and custom ROM modules in deep submicron technologies.
Lead the verification of new ROM designs and establish new design flows.
Collaborate with multi-functional teams to improve standard cell development and enhance quality checks on libraries.
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
Job description
NVIDIA's VLSI team transforms groundbreaking GPU and accelerator architectures into production silicon at the world's most advanced process nodes. Our team drives IP design, and verification for chips of unmatched complexity - billions of transistors pushing the limits of performance and power efficiency. Unlike typical VLSI roles, engineers here directly shape products that define the state of the art in AI, HPC, and autonomous systems, working at a pace and scale few organizations can match. If you want your implementation expertise to have outsized real-world impact, this is the place.
What you'll be doing:
- Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.
- Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
- Lead the function and feasibility verification of new ROM designs and set up new design flows.
- Provide creative insights to support and enhance existing tools and flows and develop new simulations to perform design margin evaluations.
- Collaborate with multi-functional teams regarding opportunities to improve standard cell develop. We will improve on our quality checks on the libraries.
What we need to see:
- MS in Electrical or Computer Engineering (or equivalent experience).
- 3+ years of experience.
- We are looking for strong background in advanced submicron process issues.
- Deep understanding of the build and verification of both conventional cell libraries and custom ROMs.
- Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools.
- Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations.
- Hands-on experience of DRC/LVS debug.
- Experience of designing and optimizing flip flops, level shifters, latches, and/or custom ROMs, register files, SRAM.
- Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus.
Ways to stand out from the crowd:
- Exposure to standard cell, memory, or custom circuit development would be beneficial.
- Experience with RTL, logic synthesis, and familiarity with place and route is preferred.
- Prior leadership experience is advantageous.
- Good interpersonal skills, quick learner, proactive, innovative, highly motivated, and committed.
Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 4, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US