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Standard Cell Design Layout Engineer Jobs (NOW HIRING)

Substrate

Standard Cell Design Lead

San Francisco, CA · On-site

$150K - $275K/yr

We are a team of world-class scientists, engineers, and technical experts building technology for ... This role requires deep expertise in digital cell design, layout, and timing characterization ...

Apple

Analog Layout Engineer

Austin, TX · On-site

$200K/yr

High Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly ... Cadence Innovus. CAD Automation experience. PCell creation experience. MSEE or Ph.D. in Electrical ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

This is a hands-on layout role with real architectural influence. You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

This is a hands-on layout role with real architectural influence. You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate ...

Nvidia

PCB Design Layout Engineer

Santa Clara, CA

We are looking for a Senior PCB Design Layout Engineer join the Hardware Layout team. NVIDIA has ... industry standards and regulations related to PCB layout and manufacturing processes. Strong ...

Nvidia

PCB Design Layout Engineer

Santa Clara, CA · On-site

We are looking for a Senior PCB Design Layout Engineer join the Hardware Layout team. NVIDIA has ... Familiarity with industry standards and regulations related to PCB layout and manufacturing ...

Nvidia

PCB Design Layout Engineer

Santa Clara, CA · On-site

We are looking for a Senior PCB Design Layout Engineer join the Hardware Layout team. NVIDIA has ... Familiarity with industry standards and regulations related to PCB layout and manufacturing ...

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Standard Cell Design Layout Engineer information

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How much do standard cell design layout engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for standard cell design layout engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Standard Cell Design Layout Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 83% Full Time, 13% Part Time, 2% Contract, and 1% Nights. Highlights an 95% Physical, 1% Hybrid, and 4% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Standard Cell Design Lead

San Francisco, CA • On-site

Substrate
1 - 10 employees
Learn more about Substrateexternal

$150K - $275K/yr

Full-time

Re-posted 18 days ago

Job description

Standard Cell Design Lead
Substrate is addressing one of the most important technological problems facing the United States. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen America's technological leadership. We are a team of world-class scientists, engineers, and technical experts building technology for the United States.
Summary
As a Standard Cell Design Lead, you will develop and optimize standard cell libraries while leading cell characterization and library validation efforts. This role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. You will work across multiple locations including external fabrication facilities. This is a full-time, onsite position.
Responsibilities
  • Lead standard cell library development including logic gates, flip-flops, and complex cells
  • Optimize cell layouts for power, performance and area across Vth's and drive strengths
  • Characterize cell library including timing, power, and noise analysis for library models
  • Develop Liberty (.lib) timing files and LEF physical abstractions for EDA tool integration
  • Collaborate with PDK and process teams to ensure cell performance meets targets
  • Implement DFM techniques and validate cells against DRC/LVS rules
  • Support all DFT fault models including cell aware, physical aware, stuck-at and transition
  • Optimize cell architectural requirements including multi-Vt and multi-channel options
  • Lead library validation and qualification across distributed design and fabrication teams

Required Qualifications
  • 10+ years experience in standard cell design, library development and characterization
  • Deep understanding of standard cell architecture, layout, and optimization strategies
  • Strong background in cell characterization and Liberty timing model generation
  • Experience with layout tools (Cadence Virtuoso, Synopsys Custom Compiler, or similar)
  • Proficiency with characterization tools and SPICE simulation for timing/power analysis
  • Proven ability to balance area, performance, and power trade-offs in cell design

Preferred Qualifications
  • Advanced degree in Electrical Engineering or related field
  • Experience with advanced node standard cells or FinFET/GAA library development
  • Background in low-power design techniques and multi-threshold voltage libraries
  • Familiarity with EDA flows and library integration requirements
  • Experience in research-driven or startup semiconductor environments

Salary Range
$150,000-$275,000 USD
Substrate is an equal opportunity employer. It provides equal employment opportunity to all applicants without regard to race, color, religion, national origin, disability, medical condition, marital status, sex, gender, age, military or veteran status, or any other characteristic protected by applicable federal, state, or local laws.
Substrate will provide reasonable accommodations to applicants with disabilities. If you need an accommodation during the hiring process, please let your recruiter know.
Applicants must be legally authorized to work in the United States. This position is not eligible for visa sponsorship.

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