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Staff Analog Design Engineer Jobs (NOW HIRING)

Analog Design Engineer

Tucson, AZ · On-site

$70 - $92/hr

Analog Design Engineer Onsite Location: Tucson, AZ Required: Secret Clearance No 1099, No third parties, no C2C, No Visas or Green Cards No exceptions (Sorry) W2 Hourly long term Contract Only $70 ...

Analog Design Engineer Onsite Location: Tucson, AZ Required: Secret Clearance No 1099, No third parties, no C2C, No Visas or Green Cards No exceptions (Sorry) W2 Hourly long term Contract Only $70 ...

Analog Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Description We are looking for qualified Analog design engineers who have a good understanding of analog circuit and CMOS Image Sensor. Candidates should have the capability to design and develop ...

We are looking for qualified Analog design engineers who have a good understanding of analog circuit and CMOS Image Sensor. Candidates should have the capability to design and develop analog circuit ...

We are looking for qualified Analog design engineers who have a good understanding of analog circuit and CMOS Image Sensor. Candidates should have the capability to design and develop analog circuit ...

Analog Design Engineer

Irvine, CA · On-site

$110K - $150K/yr

Description We are looking for Image Sensor Analog Design Engineer for design and development of next generation image sensors and related technologies. The candidate should have strong fundamentals ...

We are looking for Image Sensor Analog Design Engineer for design and development of next generation image sensors and related technologies. The candidate should have strong fundamentals in analog ...

Analog Design Engineer Santa Clara, CA- Onsite Salary: Market- FTE Start: Immediate Requires good SerDes experience Minimum Qualifications: The ideal candidate should have a minimum of MS in ...

We are looking for Image Sensor Analog Design Engineer for design and development of next generation image sensors and related technologies. The candidate should have strong fundamentals in analog ...

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Staff Analog Design Engineer information

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$77K

$186.2K

$203K

How much do staff analog design engineer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for staff analog design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Staff Analog Design Engineer, and why are they important?

To thrive as a Staff Analog Design Engineer, you need a solid background in electrical engineering, expertise in analog and mixed-signal circuit design, and typically a bachelor’s or master’s degree in a related field. Proficiency with industry-standard EDA tools like Cadence, SPICE simulation, and layout software is essential, along with familiarity with silicon process technologies. Strong analytical thinking, problem-solving, and effective communication skills help you collaborate with cross-functional teams and tackle complex design challenges. These skills and qualities are vital for creating reliable, high-performance analog circuits that meet project requirements and industry standards.

What are some common challenges faced by Staff Analog Design Engineers when working on complex integrated circuits?

Staff Analog Design Engineers often encounter challenges such as meeting stringent performance specifications while balancing power consumption, area, and cost constraints. Debugging and validating analog circuits can be particularly complex due to their sensitivity to process variations and noise. Additionally, effective collaboration with digital design teams, layout engineers, and test engineers is essential to ensure successful integration and manufacturability of the final product. Staying current with evolving IC technologies and design tools is also critical for success in this role.

What are Staff Analog Design Engineers?

Staff Analog Design Engineers are experienced professionals who design, develop, and test analog circuits and systems used in electronic devices. They are responsible for creating components such as amplifiers, filters, power management circuits, and sensors that operate using continuous electrical signals. In addition to circuit design, they often mentor junior engineers, oversee project timelines, and collaborate with cross-functional teams to ensure the successful integration of analog components into larger systems.
More about Staff Analog Design Engineer jobs
Infographic showing various Staff Analog Design Engineer job openings in the United States as of May 2026, with employment types broken down into 5% Locum Tenens, 5% As Needed, 68% Full Time, 3% Temporary, and 19% Contract. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.
Senior Staff Analog Circuit Design Engineer - SerDes

Senior Staff Analog Circuit Design Engineer - SerDes

Intel

Folsom, CA • On-site

$361K/yr

Full-time

Medical, Retirement, PTO

This job post has expired today. Applications are no longer accepted.


Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

8th of 139 rated electronics manufacturers


Job description

Job Details:Job Description: 

The Role and Impact
We areseekinga highly motivated and skilledSenior Staff Analog Circuit Design Engineerto contribute to the design, implementation, and validation of advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications.

In this role, you willparticipatein the definition, design, and verification of high-performance analog blocks and subsystems, collaborating closely with system architects, digital designers, and layout engineers.The ideal candidate is self-driven, detail-oriented, and passionate about analog design in high-speed communication systems.


Key Responsibilities

  • Design and implement advanced analog and mixed-signal circuits for 112G and 224G SerDes applications
  • Participate in the definition, design, and verification of high-performance analog blocks and subsystems
  • Engage in technical discussions and contribute to design reviews
  • Conduct post-silicon validation and performance optimization
  • Provide guidance to layout engineers and mentor junior analog designers
  • Collaborate across disciplines with system architects, digital designers, and layout teams
  • Develop innovative designs as part of a highly experienced SerDes team focused on next-generation high-speed interconnect solutions

Core Competencies

  • Good communicationand documentation skills, with a collaborative and proactive work style
  • Strong analytical thinking, hands-on debugging skills, and an eagerness to learn and shareexpertisewithin the team
  • Demonstrated ability to work effectively in cross-functional teams and contribute to technical reviews.
  • Excellent Communication Skills
Qualifications:

The Minimum qualifications arerequiredto be initially considered for this position.Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to theminimumrequirements and are considered a plus factor inidentifyingtop candidates.

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Electronics Engineering, orinaSTEMrelated field
  • 2+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications
  • Experience in one or more of the following domains: PLL, CDR, CTLE, DFE, ADC,LDO,RefGen,or Transmitter (TX) design
  • Experience withcore analog design principles, including noise, linearity, matching, and stability
  • Experience with advancedFinFETCMOS process technologies
  • Experiencewith analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent

Preferred Qualifications

  • Ph.D. in Electrical Engineering, Electronics Engineering, orinaSTEMrelated field
  • Experience withof transmitter and receiver design, CDR loops, and equalization techniques
  • Experience withnext-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD
  • Experiencewith high-speed communication standards such as PCIe (Gen4/Gen5) and Ethernet (100G/400G)
  • Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python,Tcl)
  • Experiencewith signal integrity concepts, channel modeling, and system-level link analysis
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, California, Folsom, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-361,480.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968