Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Senior ASIC Timing Engineer
Westford, MA · On-site
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$147K - $152K/yr
Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins ... Computer engineering * A minimum of 8 years of hands-on experience in ASIC STA and timing ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$147K - $152K/yr
Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins ... Computer engineering * A minimum of 8 years of hands-on experience in ASIC STA and timing ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$217K - $267K/yr
Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins ... Computer engineering * A minimum of 8 years of hands-on experience in ASIC STA and timing ...
Sr. Staff Physical Design Timing Engineer (STA)
Boston, MA · On-site
$217K - $267K/yr
Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins ... Computer engineering * A minimum of 8 years of hands-on experience in ASIC STA and timing ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
Timing Design Engineer
Waltham, MA · On-site
$116K - $203K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Timing Design Engineer
Waltham, MA · On-site
$116K - $203K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Experience with clock domain crossings (CDC) and static timing analysis (STA) * Experience with ...
Timing Design Engineer
Waltham, MA · On-site
$165K - $292K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Timing Design Engineer
Waltham, MA · On-site
$165K - $292K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
Reading, MA · On-site
$192K - $307K/yr
... and static timing analysis (STA) * Support hands-on place-and-route (P&R) for critical and high ... Collaborative, engineering-driven culture * Competitive compensation, benefits, and career growth ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
Reading, MA · On-site
$192K - $307K/yr
... and static timing analysis (STA) * Support hands-on place-and-route (P&R) for critical and high ... Collaborative, engineering-driven culture * Competitive compensation, benefits, and career growth ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
North Reading, MA · On-site
$192K - $307K/yr
... and static timing analysis (STA) * Support hands-on place-and-route (P&R) for critical and high ... Collaborative, engineering-driven culture * Competitive compensation, benefits, and career growth ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
North Reading, MA · On-site
$192K - $307K/yr
... and static timing analysis (STA) * Support hands-on place-and-route (P&R) for critical and high ... Collaborative, engineering-driven culture * Competitive compensation, benefits, and career growth ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... programming skills with TCL Preferred Qualifications Experience with large design STA and/or Timing ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... programming skills with TCL Preferred Qualifications Experience with large design STA and/or Timing ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$165K - $292K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Strong programming ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$165K - $292K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Strong programming ...
Drive timing closure, congestion analysis, power optimization, and area improvement across assigned ... Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ...
Drive timing closure, congestion analysis, power optimization, and area improvement across assigned ... Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ...
RTL Design Engineer
Waltham, MA · On-site
This is an excellent opportunity to gain valuable experience in software methods and analysis ... static timing and DFT Proven knowledge of SystemVerilog assertions, checkers, and other design ...
RTL Design Engineer
Waltham, MA · On-site
This is an excellent opportunity to gain valuable experience in software methods and analysis ... static timing and DFT Proven knowledge of SystemVerilog assertions, checkers, and other design ...
RTL Design Engineer
Waltham, MA · On-site
This is an excellent opportunity to gain valuable experience in software methods and analysis ... static timing and DFT Proven knowledge of SystemVerilog assertions, checkers, and other design ...
RTL Design Engineer
Waltham, MA · On-site
This is an excellent opportunity to gain valuable experience in software methods and analysis ... static timing and DFT Proven knowledge of SystemVerilog assertions, checkers, and other design ...
Sta Static Timing Analysis Engineer information
What is a STA static timing analysis engineer?
STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.
What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?
To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
What are some common challenges faced by STA static timing analysis engineers during project cycles?
STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.
What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Massachusetts?
For Sta Static Timing Analysis Engineer jobs in Massachusetts, the most frequently searched job titles are:
What job categories do people searching Sta Static Timing Analysis Engineer jobs in Massachusetts look for?
The top searched job categories for Sta Static Timing Analysis Engineer jobs in Massachusetts are:
What cities in Massachusetts are hiring for Sta Static Timing Analysis Engineer jobs?
Cities in Massachusetts with the most Sta Static Timing Analysis Engineer job openings:
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
6th of 247 rated software companies
Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people.
Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
What we need to see:
Ways to stand out from the crowd:
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 10, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
- You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
- Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
- Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
What we need to see:
- Great teammate
- BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing.
- Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
- Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
- Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
- Background in logic synthesis and/or logical equivalence checking (LEC).
- Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus).
- Proficiency in Python, Tcl and Make for automation and scripting tasks.
Ways to stand out from the crowd:
- Background in domain specific STA and timing convergence, such as CPUs, GPUs or Network processor implementation or SOCs.
- Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.
- Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations.
- Experience in methodology and/or flow development as well as automation.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 10, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US