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Specman Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

Lakeway, TX · On-site

$134K - $164K/yr

Specman/e expertise to a similar level. * C/C++ developing, or integrating, reference models into ... Engineering, or Computer Science. * 7 years of project-proven verification experience.

Specman Verification Engineer information

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$80K

$142.6K

$203.5K

How much do specman verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for specman verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Specman Verification Engineer jobs?

For Specman Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Specman Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Design Verification Engineer

San Diego, CA

$144K - $176K/yr

Full-time

Re-posted 11 hours ago


Job description

Company Description

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.

Job Description

Job Title : Design Verification Engineer

Job Type : Full time

Location : San Diego And Bay Area

Job Description :
Strong verification skills: test planning, problem solving, debug,
adversarial testing. Multimedia Camera Image processing, Video or graphics
hardware experience is preferred.
Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C.
Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience
and/or very strong OOPs programming experience is also a plus.
Good written and oral communications skills required.
Experience with simulation acceleration tool like Veloce/Palladium is a plus.
Skill required:
CPU, (MC: middle core, ARM architecture)
Decent knowledge of assertions.
SV and decent UVM knowledge
Code coverage.
Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.

Additional Information

All your information will be kept confidential according to EEO guidelines.