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Soc Power Performance Architect Jobs (NOW HIRING)

Qualcomm

Senior SoC Performance Architect

Santa Clara, CA · On-site +1

$196K/yr

Engineering Group, Engineering Group > SoC Architecture General Summary: We are seeking a Senior ... Experience working with firmware, BIOS, power/performance tuning, and system configuration controls.

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Soc Power Performance Architect information

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$156.5K

$168K

How much do soc power performance architect jobs pay per year?

As of Sep 10, 2026, the average yearly pay for soc power performance architect in the United States is $167,842.00, according to ZipRecruiter salary data. Most workers in this role earn between $167,000.00 and $167,000.00 per year, depending on experience, location, and employer.

What is a SoC Power Performance Architect?

SoC Power Performance Architects are specialized engineers who design, analyze, and optimize the power consumption and performance characteristics of System on Chip (SoC) devices. They work to balance energy efficiency with computing power, ensuring that chips meet both performance goals and power constraints for applications like smartphones, tablets, and embedded systems. Their responsibilities often include defining power management strategies, collaborating with hardware and software teams, and using simulation tools to validate and improve SoC architectures.

How does a SoC Power Performance Architect typically collaborate with cross-functional teams during the product development cycle?

As a Soc Power Performance Architect, you will work closely with hardware, software, and system engineering teams to define and optimize power and performance targets for system-on-chip designs. This role involves frequent collaboration in design reviews, analyzing trade-offs, and driving consensus among stakeholders to meet project objectives. You may also coordinate with validation and verification teams to ensure the implemented solutions align with the intended power and performance goals. Effective communication and teamwork are essential for navigating the complex interdependencies in modern SoC projects.

What are the key skills and qualifications needed to thrive as a SoC Power Performance Architect, and why are they important?

To thrive as a SoC Power Performance Architect, you need a strong background in electrical or computer engineering, experience with SoC design, and expertise in power and performance optimization. Familiarity with EDA tools like Synopsys, Cadence, and power analysis tools, as well as knowledge of hardware description languages such as Verilog or VHDL, is typically required. Strong analytical thinking, problem-solving abilities, and effective cross-functional communication are key soft skills for excelling in this role. These skills ensure optimal chip efficiency, successful collaboration between hardware and software teams, and the delivery of competitive, energy-efficient products.

What is the difference between Soc Power Performance Architect vs Soc Security Engineer?

AspectSoc Power Performance ArchitectSoc Security Engineer
CredentialsCertifications like CISSP, CEH, or vendor-specific certifications; strong understanding of power systems and performance metricsCertifications such as CISSP, CISA, or GIAC; focus on security protocols and threat mitigation
Work EnvironmentDesigning and optimizing power and performance systems within security operations centersImplementing and managing security measures within SOC environments
Industry UsageUsed in industries focusing on system performance and power efficiency in security settingsCommonly employed in cybersecurity and information security sectors

The Soc Power Performance Architect and Soc Security Engineer roles share a focus on security operations but differ in their core expertise. The architect specializes in optimizing power and system performance within SOCs, while the security engineer concentrates on implementing security measures. Both roles require relevant certifications and work within security environments, but their primary focus areas distinguish them in the industry.

What are popular job titles related to Soc Power Performance Architect jobs?

For Soc Power Performance Architect jobs, the most frequently searched job titles are:

Infographic showing various Soc Power Performance Architect job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 87% Full Time, 10% Part Time, and 2% Contract. Highlights an 84% Physical, 2% Hybrid, and 14% Remote job distribution, with an average salary of $167,842 per year, or $80.7 per hour.

Sr. Staff SoC Power & Performance Architect

Austin, TX • On-site

Ambiq Micro, Inc.
51 - 200 employees
Learn more about Ambiq Micro, Inc.external

$165K/yr

Full-time

Posted 18 days ago

Job description

Company Overview
Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world's lowest-power semiconductor solutions.
Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.
We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.
At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.
If that's you, join us - the intelligence everywhere revolution starts here.
This role will be on-site 5 days a week in NW Austin.
Scope
Ambiq is looking for a Sr. Staff Power & Performance Architect to help shape the architecture behind some of the industry's most power-efficient SoCs. You will drive power and performance analysis, budgeting, modeling, and debug from early architecture through silicon correlation, while defining practical architecture guidance for power management, clocking/reset, fabric, and embedded system behavior.
This role is ideal for a senior low-power SoC architect who enjoys hands-on analysis, silicon debug, architecture specification, automation, and customer-facing technical influence.
Responsibilities
  • Execute power and performance analysis across pre-silicon modeling, RTL power analysis, power-aware simulation, and post-silicon correlation.
  • Build and maintain SoC, subsystem, and use-case-level power budgets.
  • Drive variance analysis against power and performance targets, surfacing risks early.
  • Lead architectural debug of power anomalies in simulation, emulation, or silicon.
  • Trace issues from waveform to RTL to architectural intent to root cause.
  • Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.
  • Characterize power states, transitions, leakage/dynamic splits, Vmin behavior, retention, and corner behavior on first silicon.
  • Feed silicon learnings back into next-generation architecture.
  • Contribute architecture and microarchitecture specifications for power management, clocking/reset, fabric, flow sequencing, software/hardware interaction, and power models.
  • Analyze process-node tradeoffs and translate them into architectural recommendations.
  • Support use-case and test-case development.
  • Partner with physical design on power domain partitioning and UPF/power intent mapping.
  • Work with software architecture teams to define power management flows, APIs, and power manager behavior.
  • Support FPGA teams during early bring-up of power management and global flows.
  • Translate silicon power/performance capabilities into datasheet guidance, competitive positioning, and customer-facing collateral.
  • Support pre-sales, field engineering, RFQ/RFI responses, customer meetings, and customer use-case power estimation as Ambiq's P&P subject-matter expert.
Qualifications
  • BS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 7+ years of architecture experience in low-power SoC, embedded SoC, semiconductor, MCU, processor, or related silicon environments.
  • Hands-on ownership of power and/or performance analysis, budgeting, and debug.
  • Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).
  • Experience with power-aware simulation flows.
  • Strong Python and/or TCL scripting for modeling, automation, reporting, and analysis.
  • Demonstrated ability to write architecture and microarchitecture specifications that engineering teams can build from.
  • Strong written and verbal communication skills.
  • Ability to work effectively across hardware, software, physical design, validation, applications, field, marketing, and sales teams.
  • Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.
Preferred Qualifications
  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 10+ years of semiconductor or embedded SoC industry experience.
  • UPF / IEEE 1801 authoring or review experience.
  • Clocking/reset architecture experience.
  • Arm Cortex-M architecture experience.
  • Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.
  • Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.
  • Prior customer-facing, pre-sales, field, or applications engineering engagement.
  • Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent.

Must be currently authorized to work in the United States for any employer.

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