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Smart Watch Engineer Jobs (NOW HIRING)

Design Verification Engineer

Sunnyvale, CA ยท On-site

$159K - $194K/yr

Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in ... We watch out for each other and go after big goals together as a team. #LI-DNI

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

Staff Product Engineer

Seattle, WA ยท On-site

$200K - $300K/yr

CORA is an on-screen assistant that delivers real-time SOP checklists, smart reminders, and ... You'll visit dispatch centers, watch how they use the product, and use that context to drive what ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

Senior Product Engineer

Seattle, WA ยท On-site

$160K - $220K/yr

CORA is an on-screen assistant that delivers real-time SOP checklists, smart reminders, and ... You'll visit dispatch centers, watch how they use the product, and use that context to drive what ...

Senior Structural Engineer

Boston, MA ยท On-site

$109K - $148K/yr

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

Senior Structural Engineer

Boston, MA ยท On-site

$109K - $148K/yr

... smart infrastructure, we provide much more than that. We create an unshakable foundation for ... Watch Our Story:' We believe that the way we work can add meaning and value to the world. That ...

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Design Verification Engineer

Sunnyvale, CA โ€ข On-site

$159K - $194K/yr

Full-time

Re-posted 5 days ago


Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?
We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.
Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
Qualifications
  • Minimum 5 years of experience of UVM based verification on a significantly complex project.
  • Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
  • Advanced knowledge of System Verilog and the UVM methodology.
  • Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
  • Good practice of one scripting language (Perl, Python, Tcl) no preference.
  • SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
  • Familiar with C/C++.
  • Formal Verification (Model Checking, Equivalence Checking).
  • Excellent communication skills in both English and Chinese.

Culture Fit:
  • Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
  • Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
  • Hungry to learn: We are eager to see you learn new skills and grow.
  • Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.

#LI-DNI