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Sipi Jobs (NOW HIRING)

Teradar

Lead Engineer - Advanced IC Packaging

San Jose, CA · On-site

$120K - $158K/yr

Co-optimize package designs for thermal, mechanical, and physical layout performance, collaborating closely with dedicated internal SIPI, RFIC, and digital teams. * Drive material selection, DFM, and ...

New

Raytheon

Senior Electrical Engineer

Goleta, CA

$116K - $151K/yr

Signal integrity and Power Integrity (SIPI) analysis via tools such as Hyperlynx simulation for SIPI. * Electronic products testing experience using the following: Bench power supplies, signal ...

Micron

HBM SIPI, Staff Engineer

Folsom, CA

$146K - $297K/yr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of ...

Micron

HBM SIPI, Staff Engineer

Richardson, TX

$146K - $297K/yr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of ...

Micron

HBM SIPI, Principal Engineer

Folsom, CA

$175K - $309K/yr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of ...

Apple

SIPI - RF Integrity Engineer

Bodega Bay, CA

$184K - $324K/yr

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Apple

SIPI - RF Integrity Engineer

Austin, TX

$129K - $225K/yr

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Apple

SIPI - RF Integrity Engineer

Austin, TX · On-site

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Apple

SIPI - RF Integrity Engineer

Austin, TX

$129K - $225K/yr

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Apple

SIPI - RF Integrity Engineer

Bodega Bay, CA

$184K - $324K/yr

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Micron

HBM SIPI, Principal Engineer

Richardson, TX

$175K - $309K/yr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of ...

Tigua Inc

Project Manager

Albuquerque, NM · On-site

Albuquerque, NM (SIPI Campus) Reporting to: Compensation: N/A Status: Full-Time; Exempt Position Summary : The Project Manager (PM) serves as Tigua's day-to-day contract lead and primary point of ...

Apple

SIPI - RF Integrity Engineer

San Francisco, CA · On-site

Our RF Integrity (RFI) team pioneers novel methodologies to solve the most complex crosstalk and coexistence issues in highly integrated systems. We operate at the cutting edge of RF/Analog design ...

Micron Technology

HBM SIPI, Staff Engineer

Richardson, TX · On-site

$146K - $297K/yr

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of ...

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What are Sipi jobs?

Sipi jobs typically refer to roles related to the Sipi Falls region in Uganda, which can include positions in tourism, hospitality, and conservation. These jobs might involve working as a tour guide, lodge staff, or environmental conservationist. Sipi Falls is a popular tourist destination, so many jobs are centered on providing services to visitors and supporting sustainable tourism. Employment opportunities may also exist in local agriculture or community development projects. The skills required often include customer service, knowledge of the area, and sometimes language proficiency.

What is the difference between Sipi vs Data Entry Clerk?

AspectSipiData Entry Clerk
Required CredentialsTypically no formal degree, but technical skills in data managementHigh school diploma or equivalent, basic computer skills
Work EnvironmentOffice or remote, often in tech or data companiesOffice settings, administrative departments
Industry UsageUsed in tech, data management, and software companiesCommon in administrative, healthcare, and finance sectors
Job FocusManaging, processing, and analyzing dataInputting, updating, and maintaining data records

While both Sipi and Data Entry Clerk roles involve handling data, Sipi often emphasizes data management and analysis with a focus on technical skills, whereas Data Entry Clerks primarily focus on inputting and maintaining data records in administrative settings. The choice depends on the complexity of data tasks and industry context.

What are the key skills and qualifications needed to thrive as a Sipi, and why are they important?

I'm sorry, but 'Sipi' is not recognized as a real-world professional occupation, so I am unable to provide an answer.
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Sipi jobs near you
Infographic showing various Sipi job openings in the United States as of July 2026, with employment types broken down into 86% Full Time, and 14% Contract. Highlights an 100% In-person job distribution.
Manager, Package Design Engineering

Manager, Package Design Engineering

Astera Labs

San Jose, CA • On-site

Full-time

Re-posted 13 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products.
As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.
This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.
Key Responsibilities
  • Team Leadership & Execution
    • Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
    • Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
    • Lead design reviews, audits, and issue resolution through bring-up and production ramp
  • Package Design Delivery
    • Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
    • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
    • Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery
  • Cross-Functional Collaboration
    • Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
    • Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
    • Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms
  • Methodology & Automation
    • Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Materials Science, or related field
  • 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
  • 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
  • Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
  • Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
  • Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
  • Proven experience working with OSATs and substrate vendors through development and production ramp
  • Experience working with OSATs and substrate vendors through development and production ramp
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration

Preferred Qualifications
  • Master's degree in Electrical Engineering or related field
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
  • Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
  • Background in early package feasibility, platform evaluation, and technology roadmap development
  • Familiarity with chip floor planning, architecture, and system-level tradeoffs
  • Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations

The base salary range is $230,000 USD - $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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