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Signal Integrity Jobs in Oregon (NOW HIRING)

Sr. Electrical Engineer

Tualatin, OR · On-site

$110 - $150/hr

Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...

New

Sr. Electrical Engineer

Tualatin, OR · On-site

$112K - $145K/yr

Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...

Senior Analog Design Engineer

Hillsboro, OR · On-site

$220K/yr

Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis. * Background in standard and advanced package technologies. Job Type:Experienced Hire Shift:Shift ...

Security Guard

Portland, OR · On-site

$19 - $21/hr

Title Security Guard Position Summary Signal Security is seeking career-minded Security Guards ... Integrity. Team members receive respect, regular performance evaluations, pay raises tied to ...

You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule. * Performing ...

Silicon Packaging Design Engineer

Hillsboro, OR · On-site

$148K/yr

Additionally, the candidate should have at least one of the following: * 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals. * 1+ year ...

Solid understanding of high-speed design signal integrity practices * Experience with Virtuoso and Calibre is a plus * Experience using Valor is helpful NVIDIA is widely considered to be one of the ...

Senior Calibration Engineer

Tualatin, OR · On-site

$161K - $284K/yr

Knowledge of Signal Integrity concepts including eye diagrams and TDR analysis. * Experience with FPGA-based measurement systems. * Advanced statistical analysis skills. * Experience leading cross ...

Electrical Engineer, Principal

Newberg, OR · On-site

$146K - $178K/yr

Thorough knowledge of designing for signal integrity of Analog Circuits. * Working knowledge of mechanical CAD tools, such as AutoCAD and Autodesk Inventor. * Ability to create/manage a vision and ...

Electrical Engineer, Principal

Newberg, OR · On-site

$146K - $178K/yr

Thorough knowledge of designing for signal integrity of Analog Circuits. * Working knowledge of mechanical CAD tools, such as AutoCAD and Autodesk Inventor. * Ability to create/manage a vision and ...

Sr Principal RF Engineer

Beaverton, OR · On-site

$115K - $151K/yr

Background in PCB design and understanding of fabrication constraints and signal-integrity considerations. * Familiarity with on-wafer RF calibration techniques (SOL, SOLT, SOLR, TRL). * Working ...

Sr Manager, RF Design

Portland, OR · On-site

$139 - $182/hr

The role works closely with Product and Applications Engineering, Signal Integrity and RF Engineering, Operations, and Global Customer teams to deliver innovative, manufacturable, and cost-effective ...

Sr Manager, RF Design

Beaverton, OR · On-site

$139 - $182/hr

The role works closely with Product and Applications Engineering, Signal Integrity and RF Engineering, Operations, and Global Customer teams to deliver innovative, manufacturable, and cost-effective ...

Understanding system and board-level design tradeoffs for high performance NIC integration (thermal, power, signal integrity, BMC, BIOS integration). * System admin or network admin-level experience ...

Showing results 41-60

Signal Integrity information

See Oregon salary details

$134.8K

$178.2K

How much do signal integrity jobs pay per year?

As of Aug 21, 2026, the average yearly pay for signal integrity in Oregon is $175,831.00, according to ZipRecruiter salary data. Most workers in this role earn between $176,600.00 and $176,600.00 per year, depending on experience, location, and employer.

What is signal integrity and why is it important?

Signal integrity refers to the quality and reliability of electrical signals as they travel through circuits, especially at high speeds. Ensuring good signal integrity is crucial because poor signal integrity can cause data errors, timing issues, or complete circuit failure. Signal integrity engineers work to minimize issues like noise, crosstalk, reflections, and electromagnetic interference by carefully designing circuit layouts, selecting appropriate materials, and using simulation tools. This is particularly important in high-speed digital and RF systems, where even small distortions can have significant impacts.

What are common challenges faced by signal integrity engineers when working on high-speed PCB designs?

Signal Integrity engineers frequently encounter challenges such as managing crosstalk, minimizing electromagnetic interference, and ensuring signal quality over high-frequency transmission lines. Working closely with PCB layout designers and hardware engineers, they analyze and resolve issues related to impedance mismatches and timing delays. Staying updated with evolving standards and simulation tools is crucial, as continuous collaboration and troubleshooting are essential parts of the role.

What are the key skills and qualifications needed to thrive as a signal integrity engineer?

To thrive as a Signal Integrity Engineer, you need a solid background in electrical engineering principles, high-speed digital design, and electromagnetic theory, typically supported by a relevant engineering degree. Familiarity with simulation tools like HyperLynx, Cadence Sigrity, and oscilloscopes, as well as knowledge of industry standards and PCB layout software, is crucial. Strong problem-solving skills, attention to detail, and effective communication set top professionals apart in this field. These skills and qualities are vital to ensure reliable high-speed data transmission and prevent costly design issues in electronic systems.

What is the difference between Signal Integrity vs Signal Integrity Engineer?

AspectSignal IntegritySignal Integrity Engineer
CredentialsKnowledge of high-speed digital design, basic electrical engineeringSame as Signal Integrity, often with additional certifications or degrees
Work EnvironmentDesign teams, R&D labs, manufacturingDesign and analysis teams, R&D labs, manufacturing
Industry UsageFocuses on principles and analysisApplies principles to design, testing, and troubleshooting
Search IntentUnderstanding signal integrity conceptsFinding professionals or job roles in signal integrity

Signal Integrity refers to the principles and analysis of maintaining signal quality in electronic systems. A Signal Integrity Engineer applies these principles in designing, testing, and troubleshooting high-speed digital circuits. While the concepts are similar, the role of a Signal Integrity Engineer involves practical application and problem-solving in real-world projects.

What cities in Oregon are hiring for Signal Integrity jobs?

Cities in Oregon with the most Signal Integrity job openings:

Infographic showing various Signal Integrity job openings in Oregon as of August 2026, with employment types broken down into 1% As Needed, 79% Full Time, 18% Part Time, and 2% Contract. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution, with an average salary of $175,831 per year, or $84.5 per hour.

Principal Analog Circuit Design Engineer - SerDes

Intel

Hillsboro, OR

$220K/yr

Full-time

Medical, Retirement, PTO

Re-posted 22 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers


Job description

Job Details:Job Description: 

We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.

This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.

The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.

Desired traits:

Excellent communication, documentation, and presentation skills.

Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.

Demonstrated leadership in cross-functional technical discussions and decision-making.

Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving

Qualifications:

Minimum Qualifications

Master's degree in Electrical Engineering, Electronics Engineering, or related field.

8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications. Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).

Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.

Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).

Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Preferred Qualifications

Ph.D. in Electrical Engineering, Electronics Engineering, or related field.

10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.

Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.

Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.

Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).

Strong understanding of signal integrity, channel modeling, and system-level link performance.

Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews..

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968