As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... integrity. Your work will drive Intel's success in achieving power, performance, and area goals ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... integrity. Your work will drive Intel's success in achieving power, performance, and area goals ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... integrity. Your work will drive Intel's success in achieving power, performance, and area goals ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... integrity. Your work will drive Intel's success in achieving power, performance, and area goals ...
Work closely with simulation engineers to meet signal integrity (SI) and power integrity (PI) requirements for high-speed designs. * Collaborate with design-for-test (DFT) engineers to resolve test ...
Quick apply
Work closely with simulation engineers to meet signal integrity (SI) and power integrity (PI) requirements for high-speed designs. * Collaborate with design-for-test (DFT) engineers to resolve test ...
Work closely with simulation engineers to meet signal integrity (SI) and power integrity (PI) requirements for high-speed designs. * Collaborate with design-for-test (DFT) engineers to resolve test ...
Quick apply
Work closely with simulation engineers to meet signal integrity (SI) and power integrity (PI) requirements for high-speed designs. * Collaborate with design-for-test (DFT) engineers to resolve test ...
Sr. Electrical Engineer
$112K - $145K/yr
Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...
Quick apply
Sr. Electrical Engineer
$112K - $145K/yr
Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...
Sr. Electrical Engineer
Tualatin, OR · On-site
$112K - $145K/yr
Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...
Sr. Electrical Engineer
Tualatin, OR · On-site
$112K - $145K/yr
Deep expertise in signal integrity, electrical noise mitigation, and real-time interface design is essential to the expectations of this role. In addition, they should have a solid foundation in ...
Hardware Engineer II
$127K - $168K/yr
Create schematics and guide PCB layout with attention to signal integrity and power integrity * Implement and validate SPI, I2C, UART, GPIO, and other digital peripheral interfaces * Perform board ...
Quick apply
Hardware Engineer II
$127K - $168K/yr
Create schematics and guide PCB layout with attention to signal integrity and power integrity * Implement and validate SPI, I2C, UART, GPIO, and other digital peripheral interfaces * Perform board ...
Optimize layouts for noise isolation, shielding, and signal integrity, especially in mixed-signal environments Join us in shaping the future of technology. Apply today and be part of a team that ...
Optimize layouts for noise isolation, shielding, and signal integrity, especially in mixed-signal environments Join us in shaping the future of technology. Apply today and be part of a team that ...
High speed PHY System Architect
$164K - $311K/yr
Familiarity with signal integrity and power integrity analysis. * Background in analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization. Join us and work ...
High speed PHY System Architect
$164K - $311K/yr
Familiarity with signal integrity and power integrity analysis. * Background in analog layout techniques, including floor-planning, matching, shielding, and parasitic optimization. Join us and work ...
Timing Design Engineer
Beaverton, OR · On-site
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and ...
Timing Design Engineer
Beaverton, OR · On-site
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and ...
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and ...
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and ...
... and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and ...
... and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and ...
Strong understanding of signal integrity, channel modeling, and system-level link performance. Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.. Job ...
Strong understanding of signal integrity, channel modeling, and system-level link performance. Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews.. Job ...
OR · Hybrid
You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule. * Performing ...
New
Senior Analog Design Engineer
Hillsboro, OR · On-site
$220K/yr
Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis. * Background in standard and advanced package technologies. Job Type:Experienced Hire Shift:Shift ...
Senior Analog Design Engineer
Hillsboro, OR · On-site
$220K/yr
Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis. * Background in standard and advanced package technologies. Job Type:Experienced Hire Shift:Shift ...
Security Guard
Portland, OR · On-site
$19 - $21/hr
Title Security Guard Position Summary Signal Security is seeking career-minded Security Guards ... Integrity. Team members receive respect, regular performance evaluations, pay raises tied to ...
Quick apply
Security Guard
Portland, OR · On-site
$19 - $21/hr
Title Security Guard Position Summary Signal Security is seeking career-minded Security Guards ... Integrity. Team members receive respect, regular performance evaluations, pay raises tied to ...
Practical analog and power fundamentals, including signal integrity and signal switching, simple amplifier circuits and gain stages, protection circuitry, and transistor basics such as NPN devices.
New
Quick apply
Practical analog and power fundamentals, including signal integrity and signal switching, simple amplifier circuits and gain stages, protection circuitry, and transistor basics such as NPN devices.
New
Additionally, the candidate should have at least one of the following: * 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals. * 1+ year ...
Additionally, the candidate should have at least one of the following: * 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals. * 1+ year ...
OR · Hybrid
Solid understanding of high-speed design signal integrity practices * Experience with Virtuoso and Calibre is a plus * Experience using Valor is helpful NVIDIA is widely considered to be one of the ...
Senior Calibration Engineer
Tualatin, OR · On-site
$161K - $284K/yr
Knowledge of Signal Integrity concepts including eye diagrams and TDR analysis. * Experience with FPGA-based measurement systems. * Advanced statistical analysis skills. * Experience leading cross ...
Senior Calibration Engineer
Tualatin, OR · On-site
$161K - $284K/yr
Knowledge of Signal Integrity concepts including eye diagrams and TDR analysis. * Experience with FPGA-based measurement systems. * Advanced statistical analysis skills. * Experience leading cross ...
Signal Integrity information
See Oregon salary details
$134.8K - $138.7K
1% of jobs
$138.7K - $142.7K
0% of jobs
$142.7K - $146.6K
0% of jobs
$146.6K - $150.6K
0% of jobs
$150.6K - $154.5K
0% of jobs
$154.5K - $158.4K
0% of jobs
$158.4K - $162.4K
0% of jobs
$162.4K - $166.3K
0% of jobs
$166.3K - $170.3K
0% of jobs
$170.3K - $174.2K
0% of jobs
$175.2K is the 25th percentile. Wages below this are outliers.
$174.2K - $178.2K
99% of jobs
$134.8K
$178.2K
How much do signal integrity jobs pay per year?
What is the difference between Signal Integrity vs Signal Integrity Engineer?
| Aspect | Signal Integrity | Signal Integrity Engineer |
|---|---|---|
| Credentials | Knowledge of high-speed digital design, basic electrical engineering | Same as Signal Integrity, often with additional certifications or degrees |
| Work Environment | Design teams, R&D labs, manufacturing | Design and analysis teams, R&D labs, manufacturing |
| Industry Usage | Focuses on principles and analysis | Applies principles to design, testing, and troubleshooting |
| Search Intent | Understanding signal integrity concepts | Finding professionals or job roles in signal integrity |
Signal Integrity refers to the principles and analysis of maintaining signal quality in electronic systems. A Signal Integrity Engineer applies these principles in designing, testing, and troubleshooting high-speed digital circuits. While the concepts are similar, the role of a Signal Integrity Engineer involves practical application and problem-solving in real-world projects.
What are the key skills and qualifications needed to thrive as a signal integrity engineer?
What is signal integrity and why is it important?
What are common challenges faced by signal integrity engineers when working on high-speed PCB designs?

Full-time
Medical, Retirement, PTO
Re-posted 6 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 156 rated electronics manufacturers
Job description
Job Description:
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development of cutting-edge technologies that enable the integration of functional units, IP blocks, and subsystems into full chip designs. This position is at the forefront of innovation, requiring collaboration with cross-functional teams to define architecture and microarchitecture features, optimize performance, and ensure design integrity. Your work will drive Intel's success in achieving power, performance, and area goals, empowering our customers with industry-leading solutions.
The primary responsibilities for this role will include, but are not limited to:
- Develop architecture and microarchitecture specifications for the logic components and contribute to the overall system architecture decisions
- Implement specifications/designs in RTL and coordinate the work of other junior designers to deliver high-quality, complex logic blocks
- Develop behavioral models that represent analog and mixed-signal circuit blocks using SystemVerilog
- Run simulations and debug using logic, mixed-signal validation, and AMS simulation tools
- Ensure high-quality designs by using industry standard tools such as linting and CDC analysis
- Support the physical design team in implementing your designs, including synthesis and timing closure
- Work with the pre-silicon validation/verification team to develop test plans and verification collateral
- Work with post-silicon validation teams to resolve post-silicon issues
A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
- Comfortable working with a high level of independence.
Qualifications:
Minimum Qualifications:
Minimum qualifications are required to be initially considered for this position.
Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.
- +3 years of experience:
- With standard digital design concepts such as FSM design techniques
- With SystemVerilog
- With computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts
- With multiple clock-domain design
Preferred Qualifications:
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- BS degree in Electrical Engineering or Computer Engineering or similar field of study with 7+ years relevant experience OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 5+ years relevant experience.
- Able to work highly independently, guide other junior team members and make contributions that increase the productivity of the entire design team
- Excellent communication and interpersonal skills
- Experience with both logic and analog circuits as well as with analog behavioral modeling
- Knowledge of mixed-signal validation, signal, and systems analysis
- Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.)
- Experience with scripting languages e.g. Perl, bash/csh and Python is highly desirable
- Experience mentoring junior designers to deliver quality designs
- Experience using RTL quality tools such as linting and CDC analysis and supporting team adoption and usage
- Experience with low-power design, power gating, and multiple power-domain design
- Experience with writing, testing, packaging, and releasing firmware
- Experience writing, testing, and supporting front-end automation and packaging flows
- Experience using AI tools as a productivity booster in all aspects of the IP design process
- Strong analytical debugging skills, with a creative approach to problem-solving
Join us in redefining technology and engineering challenges. Apply today and become part of a team where your expertise drives meaningful change and innovation.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968