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Semiconductor Test Engineering Manager Director Jobs

Flex Ltd.

Test Engineering Manager

Dallas, TX · On-site

... Director, Design & Engineering the Test Engineering Manager will be responsible for leading the team responsible for testing substation control house projects while meeting budgetary and schedule ...

Flex Ltd.

Test Engineering Manager

Columbia, SC · On-site

Reporting to the Process Engineering Manager the Test Engineering Manager will be responsible for ... directors. * Ability to work with mathematical concepts such as probability and statistical ...

Fusion Energy Base

Test Engineering Manager

Kearny, NJ · On-site

$125 - $150/hr

Test Engineering Manager - Kearny, NJ, Technology - Manufacturing Engineering - Full‑time - On‑site About Thea Energy: Thea Energy is leveraging recent breakthroughs in stellarator physics and ...

Flex

Test Engineering Manager

Columbia, SC · On-site

Reporting to the Process Engineering Manager the Test Engineering Manager will be responsible for ... directors. * Ability to work with mathematical concepts such as probability and statistical ...

Flex

Test Engineering Manager

Fontana, CA · On-site

$122K - $168K/yr

Reporting to the Director, Design & Engineering the Test Engineering Manager will be responsible for leading the team responsible for testing substation control house projects while meeting budgetary ...

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Semiconductor Test Engineering Manager Director information

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$75K

$114.3K

$152.5K

How much do semiconductor test engineering manager director jobs pay per year?

As of Sep 9, 2026, the average yearly pay for semiconductor test engineering manager director in the United States is $114,331.00, according to ZipRecruiter salary data. Most workers in this role earn between $100,000.00 and $128,500.00 per year, depending on experience, location, and employer.

What does a semiconductor test engineering manager director do?

A Semiconductor Test Engineering Manager Director oversees the teams responsible for developing, implementing, and managing testing strategies for semiconductor devices and integrated circuits. They provide leadership in designing test processes, ensuring product quality, optimizing efficiency, and managing budgets and timelines. This role involves collaborating with R&D, product engineering, and manufacturing to ensure that products meet stringent industry standards. They also mentor engineering teams, drive continuous improvement initiatives, and often interact with customers and vendors to resolve technical challenges.

What are some common challenges faced by a semiconductor test engineering manager director, and how can they effectively address them?

Semiconductor Test Engineering Manager Directors often encounter challenges such as keeping up with rapidly evolving technology, managing cross-functional teams, and ensuring timely delivery of high-quality test solutions. Balancing resource allocation between multiple projects and maintaining close collaboration with design, manufacturing, and quality teams are also critical. Effective communication, continuous learning, and fostering a culture of innovation and accountability can help address these challenges and drive team success.

What are the key skills and qualifications needed to thrive as a semiconductor test engineering manager director, and why are they important?

To thrive as a Semiconductor Test Engineering Manager Director, you need a solid background in electrical engineering or a related field, experience in test engineering, and proven leadership abilities. Familiarity with automated test equipment (ATE), semiconductor test methodologies, and project management tools—as well as relevant certifications such as PMP—are typically expected. Strong communication, problem-solving, and team leadership skills set top candidates apart by enabling them to coordinate cross-functional teams and drive performance. These skills and qualifications are vital to ensure reliable product quality, efficient test processes, and strategic alignment in a competitive industry.
Infographic showing various Semiconductor Test Engineering Manager Director job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 85% Physical, 2% Hybrid, and 13% Remote job distribution, with an average salary of $114,331 per year, or $55 per hour.

Senior NPI Test Engineer (Semiconductor)

San Diego, CA

Elevate Semiconductor
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Elevate Semiconductorexternal

$106K - $166K/yr

Full-time

Re-posted 20 hours ago

Job description

We are seeking a Senior Test Engineer to lead New Product Introduction (NPI) for precision analog and mixed-signal integrated circuits used in memory, AI, computing, and high-performance automated test equipment (ATE) applications.

This role owns the production test strategy from first silicon through high-volume manufacturing and works closely with Design, Product Engineering, Applications, Quality, Operations, and external manufacturing partners to deliver robust, cost-effective production solutions.

Responsibilities

  • Lead NPI activities from first silicon through production release for precision analog and mixed-signal IC products.
  • Develop complete production test solutions for wafer sort and final test using Teradyne UltraFlex IGXL and associated handlers/probers.
  • Correlate bench measurements with ATE results and establish production test limits using statistical analysis and characterization data.
  • Develop and optimize production test programs for precision DACs, current source/sink products, PMICs, analog interface ICs.
  • Design, debug, and validate load boards, probe cards, sockets, and production hardware in collaboration with external vendors.
  • Drive multisite optimization, parallel testing, throughput improvement, and overall manufacturing cost reduction.
  • Perform silicon debug and root-cause analysis for design, process, package, and test related issues.
  • Work closely with IC Design during schematic reviews, silicon bring-up, and Design-for-Test (DFT) planning.
  • Support qualification, reliability, HTOL, characterization, and customer qualification activities.
  • Develop production release documentation including correlation reports, GR&R studies, guard-banding analysis, and manufacturing specifications.
  • Transfer products into OSAT and high-volume manufacturing while providing engineering support during production ramp.
  • Develop automation tools using Python, JMP, and data analytics to improve engineering productivity and manufacturing quality.

Requirements

  • Bachelor's degree in Electrical Engineering or related field
  • 6 plus years of experience in semiconductor test engineering, ideally with analog or mixed signal ICs
  • Experience with Teradyne UltraFlex and or Verigy SmartScale or PinScale platforms
  • Understanding of analog testing principles and methodologies
  • Experience with vector translation tools such as Velocity or Test Insight
  • Familiarity with scan testing, JTAG, memory BIST, and loopback techniques
  • Strong troubleshooting skills and attention to detail
  • Strong communication skills and ability to collaborate across teams

Preferences

  • Experience with test hardware development including load boards, probe cards, and sockets
  • Exposure to high volume manufacturing environments and offshore vendors
  • Experience with wafer level testing and multi-site optimization
  • Familiarity with analog simulation tools and testbench correlation
  • Interest in process improvement and test automation

The anticipated annual base salary range for this position is $106,250.00 to $166,750.00. Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.

In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.

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