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Semiconductor Packaging Engineer Flip Chip Jobs

Conductor

Packaging Engineer- Flip Chip

Boston, MA · On-site

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...

Conductor

Packaging Engineer- Flip Chip

Austin, TX · On-site

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...

Skyworks

Principal Packaging Engineer

Irvine, CA · On-site

$129K - $247K/yr

Principal Packaging Engineer Posting Start Date: 9/9/26 Job Location(s): Irvine If you are looking ... Flip-Chip Assembly * Materials Development * Related semiconductor assembly processes Desired ...

Texas Instruments

$16.50 - $21.50/hr

... semiconductor packaging technologies, including Wirebond, Flip Chip, Modules, SIPs and other ... Put your talent to work with us as a Packaging Engineering Intern! Texas Instruments will not ...

Texas Instruments

$16.50 - $21.50/hr

... semiconductor packaging technologies, including Wirebond, Flip Chip, Modules, SIPs and other ... Put your talent to work with us as a Packaging Engineering Intern ! QUALIFICATIONS Minimum ...

Fab2

Semiconductor Packaging Engineer

Austin, TX · On-site

$110K - $155K/yr

About the role As a Packaging Engineer at fab2, you'll work with a full-stack team to develop a complete process for fabricating semiconductor packaging devices. You'll be working on things like ...

Skyworks

Principal Packaging Engineer

Irvine, CA

$129K - $247K/yr

Mentor engineers and contribute to Skyworks' long-term packaging technology roadmap. Please note ... Flip-Chip Assembly * Materials Development * Related semiconductor assembly processes Desired ...

Skyworks Solutions, Inc

Sr. Packaging Engineer

Irvine, CA · On-site

$91K - $177K/yr

Relevant technical experience in semiconductor packaging technology. * Technical expertise required ... SMT, Flip Chip, Mold, & Singulation. * Knowledge of Flip Chip Bumping, WLCSP, Fan Out, Stack ...

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How much do semiconductor packaging engineer flip chip jobs pay per hour?

As of Sep 13, 2026, the average hourly pay for semiconductor packaging engineer flip chip in the United States is $42.37, according to ZipRecruiter salary data. Most workers in this role earn between $32.69 and $49.28 per hour, depending on experience, location, and employer.

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Infographic showing various Semiconductor Packaging Engineer Flip Chip job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $88,120 per year, or $42.4 per hour.

Packaging Engineer- Flip Chip

San Francisco, CA • On-site

Conductor
See more jobs at Conductorexternal

Other

Posted 25 days ago

Job description

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip).

This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and systemproductization.

Core Responsibilities:

  • Develop and optimize flip chip attach processes including bump formation,

placement, reflow, and underfill for high-performance semiconductor packages.

  • Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps)

and substrate pad finishes for robust interconnect performance.

  • Drive package integration from die to substrate, ensuring alignment, coplanarity,

and yield optimization.

  • Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding,

head-in-pillow, and interconnect defects.

  • Collaborate with substrate vendors, OSATs, and internal teams to define design

rules (pad pitch, bump pitch, keep-outs, stack-ups).

  • Lead process development for reflow profiles, flux selection, cleaning, and underfill

dispense/cure.

  • Perform root cause analysis of assembly and reliability failures using cross-

sectioning, SEM, CSAM, and other failure analysis techniques.

  • Support reliability qualification including thermal cycling, drop, mechanical shock,

and power cycling.

  • Work cross-functionally with design, reliability, thermal, and manufacturing teams

to ensure robust package performance from concept through high-volume

production.

Required Technical Skills:

  • Strong experience in flip chip packaging and assembly processes for

Deep understanding of bumping technologies (solder bumps, Cu pillar, micro-

  • bumps) and UBM/metallization systems.

Experience with underfill materials, dispense techniques, flow behavior, and cure

  • processes.

Understanding of thermo-mechanical behavior in flip chip assemblies (CTE

  • mismatch, warpage, solder fatigue, reliability risks).

Hands-on experience with failure analysis and reliability testing (cross-sections,

  • SEM, CSAM, thermal cycling).

Ability to work with OSATs and suppliers to develop and transfer assembly

  • processes into production.

Strong problem-solving skills with ability to debug yield and reliability issues in

  • manufacturing environments.

Preferred / Differentiating Skills:

  • Experience with III-V packaging, photonics packaging, and precision chip attach.

Experience with advanced packaging technologies including 2.5D interposers, 3D

  • stacking, chiplets, and CoWoS-like architectures.
  • Familiarity with bill of materials used in photonics packaging such as clear

adhesives and underfills as well as mold compounds and underfills for 2.5D

advanced packaging.

  • Familiarity with fine-pitch micro-bump and hybrid bonding approaches.
  • Experience integrating high-power or high-TDP devices with tight warpage and

thermal constraints.

  • Exposure to thermo-mechanical modeling or collaboration with simulation teams

for warpage and reliability prediction.

  • Understanding of system-level interactions (PCB attach, second-level interconnect

reliability).

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