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Rf Ic Layout Physical Design Engineer Jobs (NOW HIRING)

Qorvo, Inc.

Staff RFIC Design Engineer

Chelmsford, MA · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Bend, OR · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Hiawatha, IA · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Apopka, FL · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

San Jose, CA · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Apopka, FL · On-site

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Chandler, AZ · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Greensboro, NC · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

Design analog and RF layout * Understand device matching techniques * Excellent teamwork skills ... Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC ...

Qorvo, Inc.

Staff RFIC Design Engineer

Hillsboro, OR · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

Staff RFIC Design Engineer

Richardson, TX · On-site +1

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Qorvo, Inc.

NY · On-site

$144K - $187K/yr

Switch/LNA/RF IC Design Engineer, the design of GaAs/SOI/SiGe/CMOS based switch and LNA or RFIC ... The design, layout and evaluation of laminates to support switch characterization and development.

Apple

IC Package Design Engineer

Austin, TX · On-site

$134K/yr

... physical design and integration of advanced semiconductor packages across SoC, memory, RF, and ... Strong understanding of high-speed interface layout constraints (DDR, PCIe) and Signal/Power ...

Apple

IC Package Design Engineer

Los Angeles, CA · On-site

$146K/yr

... physical design and integration of advanced semiconductor packages across SoC, memory, RF, and ... Strong understanding of high-speed interface layout constraints (DDR, PCIe) and Signal/Power ...

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Rf Ic Layout Physical Design Engineer information

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$45K

$120.8K

$185.5K

How much do rf ic layout physical design engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for rf ic layout physical design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Rf Ic Layout Physical Design Engineer jobs?

For Rf Ic Layout Physical Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Rf Ic Layout Physical Design Engineer job openings in the United States as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Sr. Analog Physical Design Engineer

Santa Clara, CA • On-site

OmniVision Technologies
Software Development • 1 - 5K employees
Learn more about OmniVision Technologiesexternal

$156K - $160K/yr

Full-time

Re-posted 20 days ago

Job description

Job Title: Sr. Analog Physical Design Engineer
Job Duties:
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC's performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre.
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out.
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices.
Requirements:
Require Master's degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
Require 2 years of experience in CMOS image sensor IC layout design.
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications.
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P.
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such ascommon-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

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