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Remote Soc Analyst Jobs in Riverside, CA (NOW HIRING)

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Remote Soc Analyst information

See Riverside, CA salary details

$33.4K

$87.9K

$139.3K

How much do remote soc analyst jobs pay per year?

As of Jul 3, 2026, the average yearly pay for remote soc analyst in Riverside, CA is $87,851.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,800.00 and $102,800.00 per year, depending on experience, location, and employer.

What is a Remote SOC Analyst job?

A Remote SOC (Security Operations Center) Analyst is a cybersecurity professional who monitors and analyzes an organization's IT infrastructure for potential security threats, incidents, and vulnerabilities from a remote location. They use security tools like SIEM (Security Information and Event Management) systems to detect and respond to cyber threats in real time. Their responsibilities include investigating alerts, mitigating risks, and escalating critical issues to higher-level security teams. Remote SOC Analysts help protect organizations from cyberattacks while working from home or an offsite location.

What are some typical challenges faced by Remote SOC Analysts, and how are they managed?

Remote SOC Analysts often face challenges such as coordinating effectively with a distributed team, staying updated on rapidly evolving threats, and maintaining vigilance while working independently. To manage these, they leverage collaborative platforms, participate in regular virtual briefings, and use advanced monitoring and alert systems to maintain real-time awareness. Access to clear protocols and ongoing training helps analysts stay aligned on best practices and new cyber threat intelligence. Building strong communication channels with colleagues and supervisors ensures incidents are addressed efficiently and team cohesion remains high, even in a remote setting.

What are the key skills and qualifications needed to thrive in the Remote Soc Analyst position, and why are they important?

To thrive as a Remote SOC Analyst, you need a solid understanding of cybersecurity principles, incident response, and threat analysis, generally backed by a degree in computer science or related fields. Familiarity with security information and event management (SIEM) tools, intrusion detection/prevention systems (IDS/IPS), and certifications like CompTIA Security+, CISSP, or CEH is typically expected. Strong attention to detail, critical thinking, and clear, concise communication skills make candidates stand out. These competencies are vital for promptly detecting and mitigating security threats while ensuring effective remote collaboration within the security team.

What are the most commonly searched types of Soc Analyst jobs in Riverside, CA? The most popular types of Soc Analyst jobs in Riverside, CA are:
What are popular job titles related to Remote Soc Analyst jobs in Riverside, CA? For Remote Soc Analyst jobs in Riverside, CA, the most frequently searched job titles are:
What job categories do people searching Remote Soc Analyst jobs in Riverside, CA look for? The top searched job categories for Remote Soc Analyst jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Remote Soc Analyst jobs? Cities near Riverside, CA with the most Remote Soc Analyst job openings:
Remote Soc Analyst jobs near you
Infographic showing various Remote Soc Analyst job openings in Riverside, CA as of June 2026, with employment types broken down into 100% Full Time. Highlights an 38% Physical, 3% Hybrid, and 59% Remote job distribution, with an average salary of $87,851 per year, or $42.2 per hour.
Lead ASIC DFT Engineer - Remote (PST time zone) - Contract Opportunity

Lead ASIC DFT Engineer - Remote (PST time zone) - Contract Opportunity

Zodiac Solutions

Irvine, CA • Remote

Contractor

Posted 9 days ago

Job description

Title - Lead ASIC DFT Engineer

Location – Remote (must be aligned with PST time zone)

Duration – Contract Opportunity

Required Visa: Any Visa

Job Description

Key skills for Lead ASIC DFT:

please see these key words of in the project description for the profile consideration.

  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.