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Remote Eda Jobs (NOW HIRING)

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

Contribute to dbt models, lead EDA on unfamiliar datasets, and add checks that catch quality issues ... While this position is open to remote candidates across the U.S., we will prioritize those who live ...

Data Scientist

Camden, NJ · On-site +1

$109K - $150K/yr

Conduct exploratory data analysis (EDA) to identify patterns, anomalies, and key demand drivers ... Hybrid work model based in Camden, NJ (Monday & Friday remote; Tuesday-Thursday in-office) * 10-15 ...

... remote, with occasional travel to customer sites, partner meetings, and industry events. KEY ... Arm, Cadence, Synopsys ecosystem), or EDA vendor * Familiarity with the chiplet ecosystem: UCIe ...

Data Scientist

Camden, NJ · On-site +1

$109K - $150K/yr

Conduct exploratory data analysis (EDA) to identify patterns, anomalies, and key demand drivers ... Hybrid work model based in Camden, NJ (Monday & Friday remote; Tuesday-Thursday in-office) * 10-15 ...

Senior Data Analyst

$88K - $112K/yr

Did we mention we're fully remote? We found that life is just better with a fully remote workforce ... Exploratory data analysis (EDA) * Hypothesis-driven analysis * Identifying trends, patterns, and ...

Contribute to dbt models, lead EDA on unfamiliar datasets, and add checks that catch quality issues ... While this position is open to remote candidates across the U.S., we will prioritize those who live ...

Data Scientist

Camden, NJ · On-site +1

$109K - $157K/yr

... data analysis (EDA) to identify patterns, anomalies, and key demand driversInsight ... Friday remote; Tuesday Thursday in-office)10 15% travel for company and customer ...

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Remote Eda information

What is the difference between Remote Eda vs Remote Data Analyst?

AspectRemote EdaRemote Data Analyst
Required CredentialsTypically requires knowledge of EDA tools (e.g., Python, R, SQL)Requires skills in data analysis, statistics, and visualization tools
Work EnvironmentPrimarily focused on data exploration and cleaningAnalyzes data to generate reports and insights
Industry UsageCommon in data science, analytics, and research rolesWidely used across business, finance, marketing, and healthcare sectors
Search & Comparison IntentOften compared for data preparation skillsCompared for insights and reporting capabilities

Remote Eda specialists focus on exploring and cleaning data to prepare it for analysis, while Remote Data Analysts interpret data to generate reports and insights. Both roles require strong analytical skills but differ in their primary focus and tools used.

What are some common challenges faced by Remote EDA (Electronic Design Automation) engineers, and how can they be overcome?

Remote EDA engineers often face challenges such as collaborating effectively across different time zones, managing access to large datasets or computing resources, and maintaining clear communication with design and verification teams. To overcome these, it's important to utilize version control systems, secure remote access tools, and project management platforms that facilitate asynchronous updates. Regular virtual meetings and clear documentation practices also help ensure alignment and smooth progress on complex design projects.

What are the key skills and qualifications needed to thrive as a Remote EDA (Electronic Design Automation) Engineer, and why are they important?

To thrive as a Remote EDA Engineer, you need a strong background in electrical engineering, digital/analog circuit design, and experience with ASIC/FPGA development, typically supported by a relevant degree. Proficiency in EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like Python or TCL, are commonly required. Excellent problem-solving, self-motivation, and clear communication skills are vital for effective collaboration and independent work in a remote environment. These combined skills ensure efficient design workflows, high-quality deliverables, and seamless teamwork across distributed teams.

What is a Remote EDA?

A Remote EDA (Electronic Design Automation) professional is someone who uses specialized software tools to design, verify, and simulate electronic circuits and systems, all while working remotely. These professionals collaborate with engineering teams to develop integrated circuits (ICs), printed circuit boards (PCBs), and other electronic components from a remote location. Remote EDA roles require expertise in EDA tools, strong problem-solving skills, and effective communication to ensure project success despite not working on-site. This setup allows companies to access skilled talent globally and enables professionals to work from anywhere.
More about Remote Eda jobs
What cities are hiring for Remote Eda jobs? Cities with the most Remote Eda job openings:
What are the most commonly searched types of Eda jobs? The most popular types of Eda jobs are:
What states have the most Remote Eda jobs? States with the most job openings for Remote Eda jobs include:
Infographic showing various Remote Eda job openings in the United States as of July 2026, with employment types broken down into 8% Locum Tenens, 28% As Needed, 61% Full Time, 1% Part Time, and 2% Contract. Highlights an 89% Physical, 4% Hybrid, and 7% Remote job distribution.

Full-time

Posted 28 days ago


Job description

Title - Lead ASIC DFT Engineer
Location - Remote (must be aligned with PST time zone)
Contract Term - Contract
Job Description
Experience
  • 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary
  • We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
  • The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debugging.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.