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Remote Contract Game Developer Jobs in Riverside, CA

Tunabear

Peoplesoft Payroll Developer

Riverside, CA · Remote

Peoplesoft Payroll Developer * Full time contract (1099/C2C) * 100% remote (PST) Scope of Work / Responsibilities * Participate in development activities for our direct, higher education client ...

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All JobsContract Game Developer JobsRemote Contract Game Developer JobsRemote Contract Game Developer Jobs in Riverside, CA

Remote Contract Game Developer information

See Riverside, CA salary details

$33.9K

$113.2K

$187.8K

How much do remote contract game developer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for remote contract game developer in Riverside, CA is $113,164.00, according to ZipRecruiter salary data. Most workers in this role earn between $85,000.00 and $129,400.00 per year, depending on experience, location, and employer.

What is the difference between Remote Contract Game Developer vs Remote Full-Time Game Developer?

AspectRemote Contract Game DeveloperRemote Full-Time Game Developer
CredentialsPortfolio, relevant experience, possibly specific software certificationsPortfolio, relevant experience, possibly specific software certifications
Work EnvironmentProject-based, flexible hours, short-term contractsCompany-employed, fixed schedule, ongoing employment
Employer & Industry UsageFreelance platforms, indie studios, larger game companies for specific projectsGame studios, publishers, tech companies with permanent teams

Remote Contract Game Developers typically work on a project basis with flexible hours, often through freelance platforms or for specific projects. In contrast, Remote Full-Time Game Developers are employed directly by companies with a fixed schedule and ongoing employment. Both roles require similar skills and credentials but differ mainly in employment type and work structure.

What are popular job titles related to Remote Contract Game Developer jobs in Riverside, CA? For Remote Contract Game Developer jobs in Riverside, CA, the most frequently searched job titles are:
What job categories do people searching Remote Contract Game Developer jobs in Riverside, CA look for? The top searched job categories for Remote Contract Game Developer jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Remote Contract Game Developer jobs? Cities near Riverside, CA with the most Remote Contract Game Developer job openings:
Remote Contract Game Developer jobs near you
Lead ASIC DFT Engineer - Remote (PST time zone) - Contract Opportunity

Lead ASIC DFT Engineer - Remote (PST time zone) - Contract Opportunity

Zodiac Solutions

Irvine, CA • Remote

Contractor

Posted 16 days ago

Job description

Title - Lead ASIC DFT Engineer

Location – Remote (must be aligned with PST time zone)

Duration – Contract Opportunity

Required Visa: Any Visa

Job Description

Key skills for Lead ASIC DFT:

please see these key words of in the project description for the profile consideration.

  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.