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Remote Asic Rtl Design Engineer Jobs in Minneapolis, MN

skywater

CAD Engineer - Staff (PDK)

Minneapolis, MN · On-site +1

... given to remote location. The Electronic Design Automation (EDA) engineer will collaborate ... to RTL to GDSII) & IC fabrication (tape-out to post-silicon validation and testing). • ...

Actalent

Distribution Design Engineer

Saint Paul, MN · On-site +1

$34.18 - $48.83/hr

Distribution Design Engineer (Remote - Minnesota)Build the Future of Power Infrastructure Are you an experienced Distribution Design Engineer looking for an opportunity to make a meaningful impact on ...

Quest Global

Simulation Engineer - Remote

Minneapolis, MN · On-site +1

$60K - $65K/yr

Able to work effectively with design teams to develop and optimize solutions considering multi ... Demonstrated strong engineering techniques, including technical risk management. * Demonstrates ...

Quest Global

Simulation Engineer - Remote

Minneapolis, MN · Remote

$60K - $65K/yr

Able to work effectively with design teams to develop and optimize solutions considering multi ... Demonstrated strong engineering techniques, including technical risk management. * Demonstrates ...

Quest Global

Simulation Engineer - Remote

Minneapolis, MN · Remote

$60K - $65K/yr

Able to work effectively with design teams to develop and optimize solutions considering multi ... Demonstrated strong engineering techniques, including technical risk management. * Demonstrates ...

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Remote Asic Rtl Design Engineer information

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$98.1K

$156.8K

$210.8K

How much do remote asic rtl design engineer jobs pay per year?

As of Aug 3, 2026, the average yearly pay for remote asic rtl design engineer in Minneapolis, MN is $156,774.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,300.00 and $187,900.00 per year, depending on experience, location, and employer.

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Minneapolis, MN? The most popular types of Asic Rtl Design Engineer jobs in Minneapolis, MN are:
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Remote Asic Rtl Design Engineer jobs near you

CAD Engineer - Staff (PDK)

skywater

Minneapolis, MN • On-site, Remote

Other

Re-posted 22 days ago

Job description

Position Summary: 
This is a full-time permanent position ideally based in the Minneapolis, Minnesota area, though consideration will be given to remote location.  The Electronic Design Automation (EDA) engineer will collaborate effectively with cross-functional teams providing design enablement collateral for semiconductor integrated circuit (IC) technologies . The EDA engineer will be a significant technical contributor to a broad array of IC development projects, including IP development and integration, and Process Design Kit (PDK) development and release.  The ideal candidate will have strong skills in DRC coding, Calibre SVRF, or similar EDA tools and methodologies.
                                               
Major Area of Accountability:
•Development and release of PDK Design Rule checks using industry-standard EDA tools. 
•Technical liaison activities between internal teams, design houses, customers, and foundries to ensure successful development, tape-out, and manufacture of customer ICs. 
•Technical support for customers using SkyWater PDKs and IP collateral.
•Management of 3rd party PDK and IP developers to ensure correct collateral and accuracy necessary for IC development partners to effectively design into SkyWater technologies.
•Enablement and improvement of front to back-end IC design flows and manufacturing through DRC development, analysis, validation, and release. 
•Working closely with design, layout, and process engineers to understand and incorporate semiconductor technology requirements into PDKs. 
•Performing other duties as assigned.
 
Required Qualifications:
Education: BS or MS (preferred) in Electrical Engineering.
Experience and/or Training:
• 3-5 years of experience in the semiconductor industry.
• 3-5 years of experience in PDK and/or EDA development, working in or with semiconductor foundry companies.
• Solid understanding of IC design (architecture to RTL to GDSII) & IC fabrication (tape-out to post-silicon validation and testing).
• Familiarity with the EDA design flow in multiple process nodes and technologies using industry-standard EDA tools and foundry PDKs.
• Strong scripting skills: Python, Linux shell, etc.
• Fluent in written and spoken English, with excellent technical writing and verbal communication skills.
 

U.S. Person Required: This position requires compliance with the International Traffic in Arms Regulations (ITAR). All accepted applicants must be U.S. Persons. ITAR defines a U.S. Person as U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee.

 
Preferred Qualifications
Experience and/or Training:
• Significant experience with the use of or enablement of Cadence, Mentor, and Synopsys semiconductor EDA tools.
• Knowledge and experience in developing and/or using physical verification tools (DRC, ERC, LVS/PEX) and DFM tooling. 
• Experience in IC layout in Virtuoso or Allegro package design
• Experience with chemical-mechanical polishing (CMP) shape density filling techniques.
• Experience with data preparation and/or OPC methodologies.
• Customer facing experience.

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