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Remote Analog Layout Design Engineer Jobs in Fremont, CA

Infotech Sourcing

Design Engineer V

Sunnyvale, CA · On-site +1

US - Remote Job Title: Core Engineering - Design Engineer V PCB Layout Engineer, AR Product Team As a PCB Layout Engineer on Meta's AR Product Team, you will be responsible for driving world-class ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

... layout and evaluation * Drive high-speed IC design, >100GHz bandwidth in Si, SiGe and III-V ... Strong background in analog functional blocks design, including ESD, matching networks * Strong ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

... layout and evaluation * Drive high-speed IC design, >100GHz bandwidth in Si, SiGe and III-V ... Strong background in analog functional blocks design, including ESD, matching networks * Strong ...

AttoTude

Mixed-Signal CMOS IC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

... layout and evaluation * Drive high-speed interconnect design, including PAM4 SerDes >112Gbps in ... Design and optimization of Fractional-N synthesizers, multi-phase clock generation, and analog ...

Descript

Lead Design Engineer

San Francisco, CA · On-site +1

$247K - $280K/yr

Here, you'll go by the title Lead Design Engineer, report to the head of Product Design, and ... When applying, please put the word "analog" as the first word in your cover letter.

Descript

Lead Design Engineer

San Francisco, CA · On-site +1

$247K - $280K/yr

When applying, please put the word "analog" as the first word in your cover letter. About Descript ... We're hiring for a mix of remote roles and hybrid roles. For those who are remote, we have a ...

Wispr Flow

Design Engineer

San Francisco, CA · On-site +1

$220K - $350K/yr

Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:

Oklo

Hot Cell Design Engineer

Santa Clara, CA · On-site +1

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

Oklo

Hot Cell Design Engineer

Santa Clara, CA · On-site +1

Integrate robotic and remote handling technologies (e.g., manipulators, cameras, cranes, etc.) into ... We are looking for a Hot Cell Design Engineer that is: * Passionate about clean energy, fuel ...

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All JobsAnalog Layout Design Engineer JobsRemote Analog Layout Design Engineer JobsRemote Analog Layout Design Engineer Jobs in Fremont, CA

Remote Analog Layout Design Engineer information

See Fremont, CA salary details

$84.3K

$203.9K

$222.2K

How much do remote analog layout design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for remote analog layout design engineer in Fremont, CA is $203,869.00, according to ZipRecruiter salary data. Most workers in this role earn between $221,100.00 and $221,100.00 per year, depending on experience, location, and employer.

What is a remote analog layout design engineer?

A Remote Analog Layout Design Engineer is a professional who specializes in creating the physical layout of analog integrated circuits (ICs), such as amplifiers or power management chips, while working from a remote location. They use electronic design automation (EDA) tools to translate circuit schematics into detailed layouts that ensure optimal performance, manufacturability, and reliability. This role requires strong knowledge of semiconductor physics, analog circuit design principles, and layout techniques to minimize noise, crosstalk, and parasitics. Remote engineers collaborate with circuit designers and verification teams using online communication tools to ensure designs meet specifications and industry standards.

What are the key skills and qualifications needed to thrive as a remote analog layout design engineer?

To thrive as a Remote Analog Layout Design Engineer, you need expertise in analog and mixed-signal circuit layout, semiconductor device physics, and a relevant engineering degree. Proficiency with industry-standard EDA tools such as Cadence Virtuoso or Mentor Graphics, as well as knowledge of design rule checks (DRC) and layout versus schematic (LVS) verification, is essential. Strong attention to detail, effective communication, and the ability to collaborate virtually are valuable soft skills in this role. These skills ensure high-quality, manufacturable designs and efficient remote teamwork in a highly technical and precise field.

What are some common challenges faced by remote analog layout design engineers and how can they be addressed?

Remote Analog Layout Design Engineers often face challenges related to communication and collaboration, especially when coordinating with circuit designers and verification teams across different time zones. Managing design files and ensuring version control can also be more complex when working remotely. To address these challenges, it's important to utilize collaborative design tools, maintain clear documentation, and schedule regular virtual meetings to discuss project progress and resolve issues promptly. Building strong relationships with team members and being proactive in communication helps ensure smooth workflow and high-quality design outcomes.

What is the difference between Remote Analog Layout Design Engineer vs Remote Digital Layout Design Engineer?

AspectRemote Analog Layout Design EngineerRemote Digital Layout Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, relevant certificationsBachelor's or Master's in Electrical Engineering, relevant certifications
Work EnvironmentDesigning analog circuits, working with CAD tools, detailed layout workDesigning digital circuits, FPGA/ASIC layout, logic optimization
Industry UsageSemiconductor companies, integrated circuit design firmsSemiconductor companies, FPGA/ASIC design firms

Both roles involve circuit layout design but focus on different circuit types. Analog layout engineers work on continuous signal circuits, requiring precision and specialized skills, while digital layout engineers focus on logic-based circuits. The roles share similar credentials and work environments, often within the same industry sectors, but differ in technical focus and design tools.

What are popular job titles related to Remote Analog Layout Design Engineer jobs in Fremont, CA?

For Remote Analog Layout Design Engineer jobs in Fremont, CA, the most frequently searched job titles are:

What job categories do people searching Remote Analog Layout Design Engineer jobs in Fremont, CA look for?

The top searched job categories for Remote Analog Layout Design Engineer jobs in Fremont, CA are:

What cities near Fremont, CA are hiring for Remote Analog Layout Design Engineer jobs?

Cities near Fremont, CA with the most Remote Analog Layout Design Engineer job openings:

Remote Analog Layout Design Engineer jobs near you
Infographic showing various Remote Analog Layout Design Engineer job openings in Fremont, CA as of August 2026, with employment types broken down into 75% Full Time, and 25% Contract. Highlights an 100% Remote job distribution, with an average salary of $203,869 per year, or $98 per hour.

High-Speed Analog Layout Design Engineer

Celero Communications, Inc.

San Jose, CA • On-site, Remote

$239K/yr

Full-time

Posted 21 days ago

Job description

Senior to Principal High-Speed Analog Layout Design Engineer roles
Locations: Irvine, CA or San Jose, CA or remote
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
 
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
 
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
 
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
 
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
 
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
 
Note: Since we have several roles available, candidate job level will be evaluated during interview process.