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Rtl Verification Engineer Jobs (NOW HIRING)

RTL Verification Engineer

Santa Clara, CA · On-site

$158K - $193K/yr

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification . The ideal candidate will have hands-on ...

Sr. RTL Verification Engineer

Redwood City, CA · On-site

$166K - $203K/yr

We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.

Bachelor's degree in Electrical or Computer Engineering, with 12 years of experience (or 8 years with MS or 5 years with a PhD) required * 12+ years of experience in RTL verification. * Experience in ...

Bachelor's degree in Electrical or Computer Engineering, with 12 years of experience (or 8 years with MS or 5 years with a PhD) required * 12+ years of experience in RTL verification. * Experience in ...

Bachelor's degree in Electrical or Computer Engineering, with 12 years of experience (or 8 years with MS or 5 years with a PhD) required * 12+ years of experience in RTL verification. * Experience in ...

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

Wireless Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

Wireless Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

IP Verification Engineer

Austin, TX · On-site

$125 - $150/hr

Several years of hands‑on, in‑industry RTL verification experience at block and/or top level ... S. in Electrical Engineering, Computer Engineering, or equivalent. Preferred Skills * Test plan ...

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic ...

GPU Design Verification Engineer

Orlando, FL · On-site

$127K - $155K/yr

You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Description As a Graphics Core Hardware Verification Engineer, you will be tasked with the ...

GPU Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

The GPU Design Verification Engineer will be responsible for the pre-silicon RTL verification of sub-units in the Apple GPU. This includes deep understanding of the micro-architectural details of ...

GPU Design Verification Engineer

Orlando, FL · On-site

$127K - $155K/yr

You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Description As a Graphics Core Hardware Verification Engineer, you will be tasked with the ...

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RTL Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do rtl verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for rtl verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is an RTL verification engineer?

An RTL Verification Engineer is responsible for ensuring the functional correctness of digital designs at the Register Transfer Level (RTL). They develop and execute testbenches, write verification plans, and use simulation tools to identify design issues. Common methodologies include UVM (Universal Verification Methodology) and formal verification techniques. They collaborate with design and architecture teams to debug and refine chip designs before fabrication. This role is critical in preventing costly hardware bugs in silicon.

What skills and qualifications are needed to thrive as an RTL verification engineer?

To thrive as an RTL Verification Engineer, you need a solid understanding of digital design principles, proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, and a degree in electrical engineering or a related field. Experience with verification methodologies (UVM, SystemVerilog), simulation tools (ModelSim, VCS), and scripting languages (Perl, Python) is highly valuable. Strong analytical thinking, teamwork, and effective communication skills help you stand out in collaborative, deadline-driven environments. Mastering both technical expertise and interpersonal skills ensures accurate, timely validation of complex digital designs essential for successful chip development.

What are common challenges faced by RTL verification engineers, and how can they be addressed?

RTL Verification Engineers often face challenges such as identifying elusive design bugs, managing large-scale testbenches, and keeping up with evolving verification methodologies. These issues are typically addressed by using robust verification frameworks, collaborating closely with design and validation teams, and adopting automated testing and coverage-driven verification techniques. Staying current with industry trends and tool advancements can also help engineers work more efficiently. By building strong communication lines and adopting best practices, common obstacles can be overcome effectively, leading to successful project outcomes.

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Infographic showing various Rtl Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 92% Full Time, 3% Part Time, and 4% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

RTL Verification Engineer

Santa Clara, CA • On-site

$158K - $193K/yr

Other

Posted 7 days ago


Job description

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification. The ideal candidate will have hands-on experience developing and executing verification environments for debug logic, DFX features, scan/debug interfaces, and related RTL.

DFX – RTL Verification Engineer | VISA / JTAG / Debug Validation

Location: Santa Clara, CA
Duration: 12 Months

Key Responsibilities & Requirements

  • 6 – 8  years of hands-on experience in RTL Design Verification, DFX Verification, or ASIC/SoC Verification.
  • Strong experience in DFX (Design for X) verification and validation of DFX-related RTL.
  • Hands-on experience with JTAG / IEEE 1149.x architecture, TAP controllers, and boundary-scan concepts.
  • Strong knowledge of VISA (Vendor Independent Silicon Architecture) / VISA Debug and related validation methodologies.
  • Experience validating debug logic, debug access mechanisms, scan/debug interfaces, and associated RTL.
  • Strong hands-on expertise in SystemVerilog and UVM.
  • Experience developing and maintaining UVM testbenches, test scenarios, assertions, functional coverage, and verification plans.
  • Hands-on experience with simulation, waveform/debug analysis, failure investigation, and root-cause analysis.
  • Experience working within complex ASIC/SoC verification environments.
  • Good understanding of DFT/DFX concepts, scan architectures, TAP controllers, JTAG, and boundary scan.
  • Strong scripting/programming skills using Python, Perl, Tcl, or similar languages.
  • Experience with industry-standard verification and debug tools such as Synopsys VCS/Verdi, Siemens Questa/ModelSim, or equivalent is preferred.

 

Ideal Candidate

The ideal candidate should be able to independently drive DFX/VISA/JTAG verification activities, develop robust SystemVerilog/UVM-based verification environments, debug complex RTL failures, and work closely with Design, DFT, Architecture, and Silicon Validation teams.