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Principal Dft Design Engineer Jobs (NOW HIRING)

SambaNova

Principal DFT Engineer

Austin, TX · On-site

$180K - $255K/yr

About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.

Nokia

Principal SoC DFT Engineer

San Jose, CA · On-site

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network ... As a senior member of the DFT team, you will work closely with the architecture, IP design ...

Nokia

Principal SoC DFT Engineer

San Jose, CA · On-site

$159K - $296K/yr

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network ... As a senior member of the DFT team, you will work closely with the architecture, IP design ...

Micron Technology

Principal DFT Engineer, HBM

Folsom, CA · On-site

$146K - $309K/yr

Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff. * Work closely with verification, product engineering, test ...

Micron

Principal DFT Engineer, HBM

Richardson, TX · On-site

$146K - $309K/yr

Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff. * Work closely with verification, product engineering, test ...

Micron

Principal DFT Engineer, HBM

Folsom, CA · On-site

$146K - $309K/yr

Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff. * Work closely with verification, product engineering, test ...

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How much do principal dft design engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for principal dft design engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Principal Dft Design Engineer job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $147,220 per year, or $70.8 per hour.

Principal DFT Engineer (Silicon Engineering)

Austin, TX • On-site

SpaceX
Aerospace Product and Parts Manufacturing • 1 - 5K employees
Learn more about SpaceXexternal

Other

Re-posted 25 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 152 frontline employees who took The Breakroom Quiz

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
  • Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Run and debug non-timing and SDF annotated gate level simulations
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 10+ years of experience working with ASICs
  • 10+ years of experience in scan insertion and DFT setup, integration and validation

PREFERRED SKILLS AND EXPERIENCE:
  • Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
  • RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
  • Ability to solve complex problems including clock domain crossings and power optimization
  • Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
  • Familiar with advanced silicon process and technology nodes for high speed and low power consumption
  • Strong implementation or integration of design blocks using Verilog/SystemVerilog
  • Experience working with ATE testers and test teams

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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About SpaceX

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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