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Pre Silicon Validation Engineer Jobs in Oregon (NOW HIRING)

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug ... S. or M.S. in Electrical Engineering, Computer Engineering, or related field. * 10+ years of ...

Biotronik

Staff IC Design Engineer, Analog

Lake Oswego, OR · On-site

$207K/yr

Working for Micro Systems Engineering, Inc. (MSEI) means joining an elite team to work on some of ... pre-silicon verification and post-silicon validation; and partner with the IC Test group to define ...

Intel

Mixed Signal Logic Design Engineer

Hillsboro, OR · On-site

As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high ... Work with the pre-silicon validation/verification team to develop test plans and verification ...

Microsoft

Silicon Debug Engineer

Hillsboro, OR · On-site

Preferred Qualifications: * 3+ years of experience in Developing Integrated Circuits (pre-silicon ... valid passport. Lawful permanent residents, refugees, and asylees may verify status using other ...

EnCharge AI

Technical Program Manager - Embedded Software

OR · On-site +1

$200K - $250K/yr

You'll own the program plan from architecture through bring-up, pre-/post- silicon validation, and ... Drive execution across geographically distributed engineering teams and external partners as needed.

K2 Space

Senior FPGA Prototyping Engineer

OR · On-site +1

$120K - $225K/yr

This role spans the entire silicon lifecycle from pre-silicon FPGA platforms that enable early ... Develop automated validation infrastructure for silicon characterization and regression testing.

Intel

Senior Analog Design Engineer

Hillsboro, OR · On-site

$220K/yr

Validation and Optimization Develop test plans and oversee silicon characterization. Debug and ... issues during pre and post-silicon phases. Optimize designs for performance, power, and area ...

Staffingine LLC

Hardware Debug Engineer

Hillsboro, OR · On-site

$134K - $177K/yr

Hardware Debug Engineer Job Location: Hillsboro, OR Job Type: Contract ... The primary responsibility of this position entails executing the silicon validation and ...

Apple

SoC Power Spec Engineer

Beaverton, OR · On-site

As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You ... The job also involves partnering with the lab and silicon characterization/validation teams on ...

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Pre Silicon Validation Engineer information

What is a pre silicon validation engineer?

A Pre-Silicon Validation Engineer is responsible for verifying and testing semiconductor designs before they are manufactured. They work with simulation tools, emulation platforms, and testbenches to ensure that the hardware design meets functional and performance requirements. Their role involves writing validation plans, creating test scenarios, running simulations, and debugging design issues. This helps identify and fix design flaws early in the development process, reducing costly errors in later stages of production. They collaborate closely with design, verification, and software teams to ensure a smooth transition to silicon fabrication.

What are common day-to-day responsibilities for a pre silicon validation engineer?

As a Pre Silicon Validation Engineer, your typical day involves developing and executing test plans to verify digital design functionalities before manufacturing. You’ll collaborate with design, verification, and firmware teams to identify and debug issues using simulation and emulation platforms. Daily tasks often include writing and running testbenches, analyzing results, and documenting any bugs or inconsistencies found in the design. This role requires a proactive approach in communication and frequent problem-solving to ensure the product meets all specifications prior to fabrication.

What are the key skills and qualifications needed to thrive in the pre silicon validation engineer position, and why are they important?

To thrive as a Pre Silicon Validation Engineer, you need strong expertise in digital design, computer architecture, and verification methodologies, typically backed by a degree in electrical or computer engineering. Experience with hardware description languages (HDLs) like Verilog or VHDL, familiarity with simulation/emulation tools, and sometimes knowledge of scripting languages such as Python or Perl are highly valued. Analytical thinking, attention to detail, and effective communication skills are crucial for pinpointing design issues and working closely with cross-functional teams. These abilities are vital to ensure early detection and resolution of design flaws, leading to more robust and efficient chip development cycles.

What are popular job titles related to Pre Silicon Validation Engineer jobs in Oregon?

For Pre Silicon Validation Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Pre Silicon Validation Engineer jobs in Oregon look for?

The top searched job categories for Pre Silicon Validation Engineer jobs in Oregon are:

Pre Silicon Validation Engineer jobs near you
Infographic showing various Pre Silicon Validation Engineer job openings in Oregon as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 17% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 94% Physical, 1% Hybrid, and 5% Remote job distribution.

Principal ASIC Design Verification Engineer

K2 Space

OR • On-site, Remote

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 7 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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