Job Role: Pre and Post Silicon Validation Engineer Location: San Diego, CA Duration: 24 Months Pre and Post Silicon Validation Team is part of the central SoC digital hardware organization ...
Job Role: Pre and Post Silicon Validation Engineer Location: San Diego, CA Duration: 24 Months Pre and Post Silicon Validation Team is part of the central SoC digital hardware organization ...
Silicon Validation Engineer, Infra Silicon Responsibilities: * Define and own the end-to-end ... Drive correlation between pre-silicon simulation models and post-silicon measurements to close ...
Silicon Validation Engineer, Infra Silicon Responsibilities: * Define and own the end-to-end ... Drive correlation between pre-silicon simulation models and post-silicon measurements to close ...
Job Role: Pre and Post Silicon Validation Engineer Location: San Diego, CA Duration: 24 Months Pre and Post Silicon Validation Team is part of the central SoC digital hardware organization ...
Job Role: Pre and Post Silicon Validation Engineer Location: San Diego, CA Duration: 24 Months Pre and Post Silicon Validation Team is part of the central SoC digital hardware organization ...
We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips . This role heavily focuses on advanced ...
We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips . This role heavily focuses on advanced ...
Job Title: Post Silicon Validation Engineer II About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our ...
Job Title: Post Silicon Validation Engineer II About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our ...
About the role SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale ® platform. This role is ...
About the role SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale ® platform. This role is ...
We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips . This role heavily focuses on advanced ...
We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips . This role heavily focuses on advanced ...
Job Title: Post Silicon Validation Engineer II About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our ...
Job Title: Post Silicon Validation Engineer II About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our ...
This role is focused on post-silicon validation, hardware debug, automation, and regression testing for next-generation CPU, GPU, and APU technologies. The engineer will execute validation plans ...
This role is focused on post-silicon validation, hardware debug, automation, and regression testing for next-generation CPU, GPU, and APU technologies. The engineer will execute validation plans ...
NVIDIA is seeking Senior Post Silicon Validation Engineer to implement the world's leading SoC's, GPU's and ASIC's. This position offers the opportunity to have real impact in a multifaceted ...
NVIDIA is seeking Senior Post Silicon Validation Engineer to implement the world's leading SoC's, GPU's and ASIC's. This position offers the opportunity to have real impact in a multifaceted ...
Post-Silicon Systems Software Validation Engineer Location: Cupertino, CA and Austin TX (Preferred) Day-1 Onsite Experience: 8+ Years What You'll Be Doing: As a Senior Validation Engineer on our ...
Quick apply
Post-Silicon Systems Software Validation Engineer Location: Cupertino, CA and Austin TX (Preferred) Day-1 Onsite Experience: 8+ Years What You'll Be Doing: As a Senior Validation Engineer on our ...
Silicon Validation Engineer, Infra Silicon
Sunnyvale, CA · On-site
$178K - $250K/yr
... post-silicon phases • Lead pre-silicon validation planning using simulation and emulation ... engineering teams to validate host-side integration, PCIe and fabric interconnects, thermal ...
Silicon Validation Engineer, Infra Silicon
Sunnyvale, CA · On-site
$178K - $250K/yr
... post-silicon phases • Lead pre-silicon validation planning using simulation and emulation ... engineering teams to validate host-side integration, PCIe and fabric interconnects, thermal ...
This role is focused on post-silicon validation, hardware debug, automation, and regression testing for next-generation CPU, GPU, and APU technologies. The engineer will execute validation plans ...
Quick apply
This role is focused on post-silicon validation, hardware debug, automation, and regression testing for next-generation CPU, GPU, and APU technologies. The engineer will execute validation plans ...
Silicon Validation Engineer, Infra Silicon
Sunnyvale, CA · On-site
$212K - $294K/yr
... through post-silicon characterization and production qualification • Lead silicon bring-up ... engineers across the silicon validation organization, influencing long-term roadmap and team ...
Silicon Validation Engineer, Infra Silicon
Sunnyvale, CA · On-site
$212K - $294K/yr
... through post-silicon characterization and production qualification • Lead silicon bring-up ... engineers across the silicon validation organization, influencing long-term roadmap and team ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Post-silicon Validation and Debug Engineer
Hillsboro, OR · On-site
$106 - $200/hr
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Post-silicon Validation and Debug Engineer
Hillsboro, OR · On-site
$106 - $200/hr
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Intel is seeking a highly motivated and experienced Post-Silicon Validation Engineer to join our team and play a critical role in ensuring the quality and functionality of cutting-edge CPU products ...
Principal Engineer, Post-silicon Validation
$200K - $255K/yr
Principal Engineer, Silicon Validation Location: San Jose (on-site) Ayar Labs is shattering AI data ... Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed ...
Principal Engineer, Post-silicon Validation
$200K - $255K/yr
Principal Engineer, Silicon Validation Location: San Jose (on-site) Ayar Labs is shattering AI data ... Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed ...
Post Silicon Validation Engineer information
See salary details
$22.60 - $27.64
2% of jobs
$27.64 - $32.69
6% of jobs
$32.69 - $37.74
13% of jobs
$39.32 is the 25th percentile. Wages below this are outliers.
$37.74 - $42.79
13% of jobs
$42.79 - $47.84
11% of jobs
The median wage is $50.36 / hr.
$47.84 - $52.88
12% of jobs
$52.88 - $57.93
9% of jobs
$61.82 is the 75th percentile. Wages above this are outliers.
$57.93 - $62.98
13% of jobs
$62.98 - $68.03
13% of jobs
$68.03 - $73.08
6% of jobs
$73.08 - $78.13
3% of jobs
$22
$51
$78
How much do post silicon validation engineer jobs pay per hour?
What is a post silicon validation engineer?
What are the key skills and qualifications needed to thrive as a post silicon validation engineer?
What are some common challenges faced by post silicon validation engineers during the product development cycle?
What is the difference between Post Silicon Validation Engineer vs ASIC Validation Engineer?
| Aspect | Post Silicon Validation Engineer | ASIC Validation Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Post-production testing, debugging hardware, and firmware validation | Pre-silicon design verification, simulation, and functional testing |
| Industry Usage | Used after chip fabrication to ensure hardware functions correctly | Used during chip design phase to verify functionality before fabrication |
Post Silicon Validation Engineers focus on testing and debugging chips after manufacturing, ensuring hardware functions as intended. In contrast, ASIC Validation Engineers work during the design phase to verify chip functionality through simulation and pre-silicon testing. Both roles require similar educational backgrounds but differ in work environment and project timing.
What cities are hiring for Post Silicon Validation Engineer jobs?
Cities with the most Post Silicon Validation Engineer job openings:
What states have the most Post Silicon Validation Engineer jobs?
States with the most job openings for Post Silicon Validation Engineer jobs include:
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The top searched job categories for Post Silicon Validation Engineer jobs are:
Contractor
Re-posted 4 days ago
Job description
Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the "Compute" & "Connectivity" space.
Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse experience in all the relevant aspects of technology and execution. The management and its entire team, handpicked from among the best talents in the industry, can adapt to the evolving technologies and growing market challenges internationally. Insilico has very flexible business models to suit a plethora of client needs.
With a current clientele of top semiconductor companies, Insilico has a wide and diversified spectrum of service offerings in expansive domains within the ambit of Embedded Design & Software, and in almost all areas of VLSI design, from Spec-to-Silicon, on a wide range of ASICs & CPUs/GPUs in all the latest technologies, including 7nm.
Being an integral part of a larger business eco-system, Insilico has the foundation of strong financials, validated processes, robust infrastructure and a global network of reputable clientele.
Insilico's service portfolio caters to products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide range of IOTs.
Headquartered in the US, it has operations in India & APAC.
Job Role: Pre and Post Silicon Validation Engineer
Location: San Diego, CA
Duration: 24 Months
Pre and Post Silicon Validation Team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The Validation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking candidates who are familiar with pre-silicon test development and post-silicon bring-up and validation.
Candidate will have a minimum of 3 years of SW/FW experience working in emulation and silicon environments.
Candidates are expected to have experience in:
- Low Level software development in C and Assembly.
- Debugging low level software and hardware issues.
- Implementing drivers and test content.
- Debug tools including JTAG, Logic Analyzer, Oscilloscope, etc., and kernel debuggers.
- Emulation environments for development and debug.
- Basic understanding of power and performance.
- Knowledge of SOC architecture and in-depth knowledge of at least one sub system (CPU, Power Management, Security IPs, System Performance, Clocks, DDR, etc.)
- Good communication skills and ability & desire to work in a cross-functional team environment.
Experience with post-silicon enabling and bring-up. Understanding of coherency and concurrency in modern SoC architectures.
Experience with at least one of: Perl, Python, TCL, C++, or Java. Industry experience preferred but not required. All your information will be kept confidential according to EEO guidelines.