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Physical Design Engineer Internship Jobs in Spring Grove, IL

IEA

Senior Design Engineer

Kenosha, WI

The Sr. Design Engineer will be responsible for carrying out the duties of the Design Engineering ... Physical Demands: Maximum lifting requirement (pounds): 10 (seldom). Maximum moving requirement ...

Astec Industries

Design Engineer

Burlington, WI

We offer programs that support physical safety, as well as benefits and resources to enhance total ... Administer design history and practice proper engineering document control processes to ensure ...

Astec Industries

Design Engineer

Burlington, WI · On-site

We offer programs that support physical safety, as well as benefits and resources to enhance total ... Administer design history and practice proper engineering document control processes to ensure ...

MacLean-Fogg

Senior Tool Design Engineer

Mundelein, IL · On-site

$43.27 - $52.88/hr

The Senior Tool Design Engineer is also responsible for mentoring junior engineers, providing ... Virtual physical therapy through Hinge Health. * On-demand access to earned wages through PayActiv.

Cadence Design Systems Inc.

Lead Design Engineer

Cary, IL · On-site

$104K - $136K/yr

Cadence's employee-friendly policies focus on the physical and mental well-being of employees ... Interface with Front End RTL design teams and Back End Verification teams Position Requirements ...

Cadence Design Systems, Inc.

Application Engineer

Cary, IL · On-site

$74K - $137K/yr

The opportunity to learn from the technical experts, sales and application engineers who provide ... Digital physical design and implementation * Sign-off for timing, IR drop, power analysis, SI ...

Eliyan

CAD - Staff AMS CAD Engineer

Mundelein, IL

As an Eliyan Staff AMS CAD Engineer , you will be working at a fast-paced startup creating ... Setup PV Flows - Establish and maintain Physical Verification flows including FILL, DRC, LVS, PERC ...

Danaher

Software Engineer Internships

Kenosha, WI · On-site

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

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All JobsPhysical Design Engineer JobsPhysical Design Engineer Internship JobsPhysical Design Engineer Internship Jobs in Spring Grove, IL

Physical Design Engineer Internship information

See Spring Grove, IL salary details

$95.4K

$142.1K

How much do physical design engineer internship jobs pay per year?

As of Aug 1, 2026, the average yearly pay for physical design engineer internship in Spring Grove, IL is $139,987.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,600.00 and $140,600.00 per year, depending on experience, location, and employer.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

What are Physical Design Engineer internships?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What are some typical projects or tasks a Physical Design Engineer intern can expect to work on during their internship?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.
What are the most commonly searched types of Physical Design Engineer jobs in Spring Grove, IL? The most popular types of Physical Design Engineer jobs in Spring Grove, IL are:
What cities near Spring Grove, IL are hiring for Physical Design Engineer Internship jobs? Cities near Spring Grove, IL with the most Physical Design Engineer Internship job openings:
Physical Design Engineer Internship jobs near you

PD - IP Lead - Sr Staff, Physical Design

Eliyan

Mundelein, IL

$138K - $142K/yr

Full-time

Re-posted 22 days ago

Job description

Join the leading chiplet startup! As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV – DRC, LVS, Antenna). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.
Responsibilities:
  • Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.
  • Lead mixed signal placement and routing, enforcing analog keepouts, shielding, and DRC aware methodologies while integrating digital logic cleanly.
  • Own system and block integration for floorplanning, power, placement, CTS, and constraints, ensuring consistent interfaces across hierarchy and reuse
  • Drive end to end IP physical implementation from RTL handoff through GDSII, managing iterations, ECOs, and closure plans across corners
  • Develop and maintain block specific flow customizations for synthesis, PNR, EM IR, STA, and physical verification to improve QoR and predictability
  • Deliver robust constraints methodology, pushing timing intent from system to block and back, maintaining mode and corner correctness for signoff
  • Run and close subsystem signoff including STA, EM IR, SI, DRC, LVS, antenna, and metal fill, meeting reliability and manufacturability requirements
  • Optimize clock architecture and CTS for skew, latency, and power, including skew group definitions and balancing across library corners
  • Collaborate with front end, DFT, packaging, and manufacturing to resolve integration risks, test mode impacts, and physical interface requirements
  • Provide clear status, risk, and mitigation reporting to leadership, using metrics driven dashboards for PPA, convergence, and schedule predictability
Minimum Qualifications:
  • Expertise in physical design, timing closure, and signoff for small to large ASIC IP blocks, including mixed signal integration and subsystem closure ownership
  • Strong hands-on experience with floorplanning, power planning, placement, CTS, routing, EM IR, STA, and PV signoff across MMMC scenarios
  • Proven ability to improve flows through automation and scripting, with disciplined debug skills and data driven QoR and runtime optimization mindset
  • Excellent cross functional leadership and communication skills to drive alignment, technical reviews, and closure decisions under aggressive timelines

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.