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Physical Design Engineer Intern information

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$9

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$26

How much do physical design engineer intern jobs pay per hour?

As of Sep 7, 2026, the average hourly pay for physical design engineer intern in Springdale, AR is $17.08, according to ZipRecruiter salary data. Most workers in this role earn between $14.23 and $18.51 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What job categories do people searching Physical Design Engineer Intern jobs in Springdale, AR look for?

The top searched job categories for Physical Design Engineer Intern jobs in Springdale, AR are:

What cities near Springdale, AR are hiring for Physical Design Engineer Intern jobs?

Cities near Springdale, AR with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Springdale, AR as of June 2026, with employment types broken down into 80% Full Time, 19% Part Time, and 1% Temporary. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $35,528 per year, or $17.1 per hour.

ASIC Physical Design Lead

Niobiummicrosystems

Fayetteville, AR • On-site

$140 - $210/hr

Other

Medical, Dental, Vision, Retirement

Posted 5 days ago

Job description

About Niobium

At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.

Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.

About This Role

We are seeking a highly experienced ASIC Physical Design to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 8+ years of hands‑on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.

In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power‑efficient silicon across cutting edge technology nodes.

Responsibilities End-to-End Physical Implementation Leadership
  • Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.
  • Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.
Floorplanning & SoC Integration
  • Architect and execute floorplanning strategies for large, hierarchical SoCs, including:
    • IP integration and macro placement
    • Physical partitioning and hierarchy definition
    • Power grid architecture and clock distribution topology
    • DIE size, aspect ratio, and physical constraints
  • Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.
Place & Route + Timing Closure
  • Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).
  • Drive timing convergence across corners, modes, voltage domains, and operating conditions.
  • Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.
Clocking, Power, and Sign-Off
  • Implement CTS and drive skew, latency, and clock power optimization.
  • Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).
  • Integrate and validate low power methodologies, including UPF/CPF flows.
Cross-Functional Collaboration & Quality Ownership
  • Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
  • Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
  • Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.
Leadership & Mentorship
  • Provide technical leadership to a team of junior and mid-level physical designers.
  • Mentor, coach, and guide engineers in methodology, debug, and best practices.
  • Champion continuous improvement across flows, scripts, and design methodology.
Key Qualifications Education
  • BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. (Advanced degree preferred for leadership roles.)
Required Technical Expertise
  • 8+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology nodes (16nm -> 3nm preferred).
  • Deep expertise in:
    • Floorplanning
    • Place & Route
    • CTS
    • STA/Timing Closure
    • Physical verification & sign-off
    • Low power design and UPF
  • Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
  • Solid understanding of RTL-to-GDS flows, design architecture trade‑offs, and SoC integration complexities.
  • Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
Required General Skills
  • Strong communication skills—able to articulate technical decisions across cross-functional teams.
  • Highly motivated, proactive, and able to operate effectively in a distributed team environment.
  • Comfortable owning schedules, deliverables, and quality in a fast‑moving development cycle.
  • Exceptional analytical, debugging, and problem‑solving skills with a meticulous attention to detail.
Location

Niobium is headquartered in Columbus, Ohio with additional locations in Fayetteville, Arkansas, Portland, Oregon, and Dayton, Ohio. We will not be limited by geography for the right candidate.

Benefits

Niobium offers a highly competitive benefits program to support employees and their families, including:

  • Competitive salaries
  • Equity in the form of Incentive Stock Options (ISO)
  • Employer paid medical insurance plan
  • Health Savings Account (HSA) with employer contributions
  • Dental and vision reimbursement account (HRA)
  • 401(k) retirement plan with employer match
  • Flexible work location with remote options
  • Flexible time off
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