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Physical Design Engineer Intern Jobs in Reston, VA

Prescient Edge

Junior Engineer Intern

Mclean, VA · On-site

Job Title Junior Engineer Intern Location McLean, VA 22102 US (Primary) Category Research ... physical science from an accredited college or university. * Must have excellent interpersonal ...

CRI

Design Engineer - Physical Security

Mclean, VA · On-site

$85K - $100K/yr

Design Engineer CRI is looking to hire a Design Engineer in the Washington DC, Virginia, Maryland ... integrated physical and cybersecurity solutions and cutting-edge IT services, that elevate ...

Leidos

Data Engineer Intern

Fort Belvoir, VA · On-site

$41K - $75K/yr

The intern will gain hands-on experience supporting advanced Research & Development (R&D) ... Adhere to all physical security, information security, and property accountability requirements ...

Imperative Systems

Design Engineer

Alexandria, VA

You will develop complete engineering packages at progressive levels of detail (30%, 80%, 90%, and final design), incorporating physical security infrastructure including intrusion detection, CCTV ...

Imperative Systems

Design Engineer

Alexandria, VA

You will develop complete engineering packages at progressive levels of detail (30%, 80%, 90%, and final design), incorporating physical security infrastructure including intrusion detection, CCTV ...

Giesecke & Devrient

UICC Engineering Intern

Dulles, VA

$16.50 - $21.50/hr

The UICC Engineering Intern will assist the UICC Engineering department in various projects and ... Design, code and validate mobile/desktop internal/external software * Analyze and document current ...

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Physical Design Engineer Intern information

See Reston, VA salary details

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How much do physical design engineer intern jobs pay per hour?

As of Jun 20, 2026, the average hourly pay for physical design engineer intern in Reston, VA is $20.09, according to ZipRecruiter salary data. Most workers in this role earn between $16.78 and $21.78 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a Physical Design Engineer Intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What does a Physical Design Engineer Intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are popular job titles related to Physical Design Engineer Intern jobs in Reston, VA? For Physical Design Engineer Intern jobs in Reston, VA, the most frequently searched job titles are:
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What cities near Reston, VA are hiring for Physical Design Engineer Intern jobs? Cities near Reston, VA with the most Physical Design Engineer Intern job openings:
Physical Design Engineer Intern jobs near you
Sr Physical Design Engineer (Manassas, VA), Onsite with Active Secret Clearance

Sr Physical Design Engineer (Manassas, VA), Onsite with Active Secret Clearance

Encore Semi, Inc.

Manassas, VA • On-site

$170K - $210K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Physical Design Engineer (ASIC/SoC) - Onsite
Clearance Requirement: Active Secret Clearance (or ability to obtain and maintain one)
About the Role
Are you ready to design the future of aerospace and defense technology? We are looking for a talented and highly motivated Physical Design Engineer to join our Advanced Microelectronics team. In this role, you will play a critical part in the development of next-generation ASICs and SoCs that power mission-critical systems.
Own the physical implementation of complex, high-performance, and low-power designs from netlist through GDSII tape-out. Working alongside a collaborative team of digital design, verification, and systems engineers, you will leverage industry-leading EDA tools to ensure our silicon meets the rigorous performance, power, and area (PPA) targets required for national security applications.
Key Responsibilities
  • Netlist-to-GDSII Execution: Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
  • Timing Closure: Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
  • Power & Reliability Analysis: Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
  • Physical Verification: Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
  • Methodology Improvement: Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.
Required Qualifications
  • Clearance: Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
  • Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
  • Experience: Proven industry experience in ASIC/SoC physical design and tape-out cycles.
  • Tool Proficiency:  Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
    • Deep knowledge of STA and sign-off timing closure using PrimeTime.
    • Experience with EM/IR analysis using Redhawk.
    • Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
  • Scripting: Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.
Problem Solving: Exceptional analytical skills and the ability to debug complex layout, timing, or integration issues autonomously.
The anticipated annual base salary for this position is between $170,000 to $210,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.