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Physical Design Engineer Intern Jobs in Canton, MA

Level99 Entertainment

Design Engineer

Boston, MA

$90K - $120K/yr

OVERVIEW The Design Engineer is responsible for the development, design, and planning for best-in-class physical game content. Level99 Engineers identify critical aspects of new challenges and create ...

Level99 Entertainment

Design Engineer

Boston, MA · On-site

$90 - $120/hr

OVERVIEW The Design Engineer is responsible for the development, design, and planning for best-in-class physical game content. Level99 Engineers identify critical aspects of new challenges and create ...

Level99 Entertainment

Design Engineer

Boston, MA · On-site

$90K - $120K/yr

OVERVIEW The Design Engineer is responsible for the development, design, and planning for best-in-class physical game content. Level99 Engineers identify critical aspects of new challenges and create ...

Level99 Entertainment

Design Engineer

Boston, MA · On-site

$90K - $120K/yr

OVERVIEW The Design Engineer is responsible for the development, design, and planning for best-in-class physical game content. Level99 Engineers identify critical aspects of new challenges and create ...

Apple Inc.

Timing Design Engineer

Waltham, MA · On-site

$116.40 - $203/hr

... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ... Bachelors of Science in Electrical Engineering. Preferred Qualifications * Proven knowledge of the ...

NEFCO Service Divisions LLC

Design Engineer

Canton, MA · On-site

Responsible for preparing and/or coordinating the preparation of the design and engineering on ... Experience with wastewater treatment, desalination, and HVAC Physical Requirements: * Prolonged ...

NEFCO

Design Engineer

Canton, MA · On-site

Responsible for preparing and/or coordinating the preparation of the design and engineering on ... Experience with wastewater treatment, desalination, and HVAC Physical Requirements: * Prolonged ...

NEFCO Service Divisions LLC

Design Engineer

Canton, MA · On-site

Responsible for preparing and/or coordinating the preparation of the design and engineering on ... Experience with wastewater treatment, desalination, and HVAC Physical Requirements: * Prolonged ...

SiFive

Power Management Design Engineer

Boston, MA · On-site

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU ... Work with a physical implementation team to implement and optimise physical design to meet ...

SiFive

Power Management Design Engineer

Boston, MA · On-site

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU ... Work with a physical implementation team to implement and optimise physical design to meet ...

SiFive

Power Management Design Engineer

Boston, MA · On-site

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU ... Work with a physical implementation team to implement and optimise physical design to meet ...

Russell Tobin

Mechanical Design Engineer

Burlington, MA · On-site

$32/hr

Product Engineer - Mechanical / Design Engineering Location : Burlington, MA Duration : Through the ... physical disability, mental disability, reproductive health decision making, medical condition ...

New

Apple

Timing Design Engineer

Waltham, MA · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in Canton, MA

Physical Design Engineer Intern information

See Canton, MA salary details

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How much do physical design engineer intern jobs pay per hour?

As of Sep 3, 2026, the average hourly pay for physical design engineer intern in Canton, MA is $20.42, according to ZipRecruiter salary data. Most workers in this role earn between $17.02 and $22.12 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What cities near Canton, MA are hiring for Physical Design Engineer Intern jobs?

Cities near Canton, MA with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Canton, MA as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 17% Part Time, 4% Contract, and 1% Nights. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution, with an average salary of $42,480 per year, or $20.4 per hour.

Sr. Staff Physical Design Timing Engineer (STA)

Lightmatter

Boston, MA • On-site

$217K - $267K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 25 days ago

Job description

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.
Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter!
If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.
Lightmatter is (re)inventing the future of computing with light!
About this role
We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.
In this job you will be responsible for timing constraints development, STA and timing closure on leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.
Responsibilities
  • Drive the STA sign-off for our flagship Silicon photonics chips at various technology nodes.
  • Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
  • Collaborate with the architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
  • Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
  • Run full-chip STA and accurately project the timing summary across scenarios.
  • Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
  • Document best practices and lessons learned to drive continuous improvements in future projects.

Qualifications:
  • Bachelor's degree in Electrical Engineering or Computer engineering
  • 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
  • Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
  • Well versed with scripting languages like TCL and Python, PERL, or Shell
  • Strong problem solving skills with attention to every technical aspect
  • Be a strong team player with clear and precise communication skills

Preferred Qualifications:
  • Master's degree in Electrical Engineering or Computer engineering
  • A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools

We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data.
Salary Range: total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.
$217,000-$267,000 USD
Benefits
  • Comprehensive Health Care Plan (Medical, Dental & Vision)
  • Retirement Savings Matching Program
  • Life Insurance (Basic, Voluntary & AD&D)
  • Generous Time Off (Vacation, Sick & Public Holidays)
  • Paid Family Leave
  • Short Term & Long Term Disability
  • Training & Development
  • Commuter Benefits
  • Flexible, hybrid workplace model
  • Equity grants (applicable to full-time employees)

Benefits eligibility may vary depending on your employment status and location. Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.
Export Control
Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.

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