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Phd In Analog Chip Design Jobs in California (NOW HIRING)

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$120K - $171K/yr

... development and chip design in the Optical Modules Group (OMG) located in Sunnyvale, CA ... PhD 3+ years Responsibilities * Install, customize and support external vendor PDK's for both SiGe ...

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA

$237K/yr

Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip ... PhD 3+ years Advancing connectivity to secure a brighter world. Nokia is a global leader in ...

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Conduct design and development of image sensor technologies in advanced sub-micron node, including ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA

$156K - $160K/yr

Conduct design and development of image sensor technologies in advanced sub-micron node, including ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

Teledyne FLIR LLC

Analog Design Engineer

Goleta, CA · On-site

$113K - $151K/yr

Performs design trade studies and contributes to chip-level architectural decisions. Performs ... S., or PhD in EE or Physics desired * 8+ years of experience in IC design * Circuit topology

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Phd In Analog Chip Design information

What is a PhD in analog chip design?

A PhD in Analog Chip Design is a doctoral degree focused on the research, development, and innovation of analog integrated circuits and systems. Students in this program study advanced concepts in analog electronics, including circuit theory, semiconductor device physics, and mixed-signal design. The program typically involves original research that contributes to advancements in areas like low-power design, sensor interfaces, or high-frequency circuits. Graduates are prepared for careers in academia, research institutions, or advanced engineering roles in the semiconductor industry.

What are the key skills and qualifications needed to thrive as a PhD in analog chip design?

To thrive as a PhD in Analog Chip Design, you need deep expertise in analog and mixed-signal circuit design, semiconductor physics, and strong mathematical skills, typically supported by a doctorate in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence, SPICE simulation software, and experience with CMOS process technologies is vital. Strong problem-solving abilities, attention to detail, and effective communication skills help you excel in research, collaboration, and documentation. These skills ensure innovative, reliable chip designs that meet industry standards and drive advancements in electronics.

What are common challenges faced by professionals with a PhD in analog chip design when transitioning from academia to industry roles?

Professionals with a PhD in Analog Chip Design often encounter challenges such as adapting to fast-paced project timelines, aligning research-driven approaches with practical product development needs, and learning to collaborate closely with multidisciplinary teams including digital engineers, layout designers, and product managers. Unlike academic research, industry roles usually require a strong focus on manufacturability, cost constraints, and adherence to strict design specifications. Building effective communication skills and understanding the broader product lifecycle are key to a smooth transition and career growth.

What is the difference between Phd In Analog Chip Design vs Analog IC Design Engineer?

AspectPhd In Analog Chip DesignAnalog IC Design Engineer
Required CredentialsPhD in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentResearch labs, academia, or R&D divisions of companiesDesign teams within semiconductor or electronics companies
Industry UsageAcademic research, advanced R&D, or specialized industry rolesProduct development, circuit design, and manufacturing

The main difference is that a Phd In Analog Chip Design typically involves advanced research, theoretical work, and development of new concepts, often in academic or R&D settings. In contrast, an Analog IC Design Engineer focuses on practical circuit design, implementation, and production within industry settings. Both roles require strong knowledge of analog circuits, but the PhD emphasizes research and innovation, while the engineer role emphasizes application and product development.

What are popular job titles related to Phd In Analog Chip Design jobs in California?

For Phd In Analog Chip Design jobs in California, the most frequently searched job titles are:

What job categories do people searching Phd In Analog Chip Design jobs in California look for?

The top searched job categories for Phd In Analog Chip Design jobs in California are:

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Cities in California with the most Phd In Analog Chip Design job openings:

Phd In Analog Chip Design jobs near you
Infographic showing various Phd In Analog Chip Design job openings in California as of August 2026, with employment types broken down into 74% Full Time, and 26% Contract. Highlights an 100% In-person job distribution.

Senior Analog EDA/CAD ASIC Engineer

Nokia

Sunnyvale, CA • On-site

$120K - $171K/yr

Full-time

Medical, Dental, Life, Retirement, PTO

Re-posted 4 days ago

Nokia rating

7.9

Company rating: 7.9 out of 10

Based on 6 frontline employees who took The Breakroom Quiz

30th of 99 rated telecommunications companies

Job description


High-Speed Analog EDA/CAD Engineer:
Brief Description: Full-time position.
Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical Modules Group (OMG) located in Sunnyvale, CA.
Description:
Infinera is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow including foundry interface, PDK installation and support, tool evaluation and installation, layout, archive and tapeout. The engineer must be an expert in analog and mixed-signal circuit design flows and tools. Tasks will include significant tool and PDK customization and design team support. The self-motivated engineer must be able to anticipate problems and devise effective solutions.
Responsibilities:
  • Install, customize and support external vendor PDK's for both SiGe and CMOS processes
  • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10-40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
  • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
  • Execute and support layout efforts including archive and tapeout processes

Minimum Expertise Requirements:
  • Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate superior critical thinking skills, problem solving capabilities and engineering judgment.
  • Fluent with analog EDA front and back end tools
    • Cadence Virtuoso, ADE
    • Strong SKILL programming a must
    • Mentor Calibre (end user support and rule deck writing)
  • Detailed understanding of advanced high-speed analog & mixed-signal layout concepts
  • FlexLM license management
  • Strong UNIX/Linux knowledge
  • Not required but preferred
    • Perforce
    • Ocean scripting and advanced modelling and simulation knowledge
    • Linux OS support

Minimum Experience Requirements:
  • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
  • IC Technologies: High-speed IC technologies, including CMOS and bipolar.
  • IC Design Software:
    • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
    • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
  • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
  • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly.

Education Requirements:
  • BS 5+ years
  • MS 4+ years
  • PhD 3+ years

Responsibilities
  • Install, customize and support external vendor PDK's for both SiGe and CMOS processes
  • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10-40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
  • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
  • Execute and support layout efforts including archive and tapeout processes

Qualifications
  • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
  • IC Technologies: High-speed IC technologies, including CMOS and bipolar.
  • IC Design Software:
    • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
    • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
  • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
  • Work Environment: Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly.

About Us
Advancing connectivity to secure a brighter world.
Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we're advancing connectivity to secure a brighter world.
Learn more about life at Nokia.
Our recruitment process
We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.
If you're interested in this role but don't meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.
The length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.
About the Team
Some of our benefits in US:
  • Corporate Retirement Savings Plan
  • Health and dental benefits
  • Short-term disability, and long-term disability
  • Life insurance, and AD&D - Company paid 2x base pay
  • Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child)
  • Paid time off for holidays and Vacation
  • Employee Stock Purchase Plan
  • Tuition Assistance Plan
  • Adoption assistance
  • Employee Assistance Program/Work Life Resource Program

The above benefits exclude students.
Disclaimer for US/Canada
Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity. Check the salary ranges in the job info section for this role.
All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.

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