Lead package-level design reviews and own the package design technical roadmap. Basic ... Qualifications * B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials ...
Lead package-level design reviews and own the package design technical roadmap. Basic ... Qualifications * B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials ...
Senior Engineer Package Designer
$190K - $220K/yr
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
Quick apply
Senior Engineer Package Designer
$190K - $220K/yr
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package ...
Package Design Engineer - Signal and Power Integrity (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
The Package Design Engineer will provide technical direction for package electrical integrity strategy, package and PCB constraints, supplier design reviews, package substrate and board-level ...
Package Design Engineer - Signal and Power Integrity (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
The Package Design Engineer will provide technical direction for package electrical integrity strategy, package and PCB constraints, supplier design reviews, package substrate and board-level ...
Lead package-level design reviews and own the package design technical roadmap. Basic ... Qualifications * B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials ...
Lead package-level design reviews and own the package design technical roadmap. Basic ... Qualifications * B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials ...
Package Design Engineer - Signal and Power Integrity (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
The Package Design Engineer will provide technical direction for package electrical integrity strategy, package and PCB constraints, supplier design reviews, package substrate and board-level ...
Package Design Engineer - Signal and Power Integrity (TERADYNE, Agoura Hills, CA)
Agoura Hills, CA · On-site
The Package Design Engineer will provide technical direction for package electrical integrity strategy, package and PCB constraints, supplier design reviews, package substrate and board-level ...
Senior IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Senior IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site +1
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site
$230.40 - $322.56/hr
Design and analyze power delivery networks using HFSS to meet power integrity targets.Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures.Collaborate with RFIC ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site
$230.40 - $322.56/hr
Design and analyze power delivery networks using HFSS to meet power integrity targets.Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures.Collaborate with RFIC ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Senior IC Package Design Engineer - TeraWave
San Diego, CA · On-site +1
$230K - $322K/yr
Design and analyze power delivery networks using HFSS to meet power integrity targets. * Model and characterize RF and mmWave packaging with HFSS simulation tools and procedures. * Collaborate with ...
Advanced Packaging Engineer
Mountain View, CA · On-site
$160K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
Advanced Packaging Engineer
Mountain View, CA · On-site
$160K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
Principal IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site
$230K - $323K/yr
You will be responsible for managing the entire product cycle of package development, from design to production. This team will conduct package-level electromagnetic (EM), signal integrity (SI), and ...
Principal IC Package Design Engineer - TeraWave
Bodega Bay, CA · On-site
$230K - $323K/yr
You will be responsible for managing the entire product cycle of package development, from design to production. This team will conduct package-level electromagnetic (EM), signal integrity (SI), and ...
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
Packaging Design Engineer I
San Jose, CA · On-site
$159K/yr
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
Packaging Design Engineer I
San Jose, CA · On-site
$159K/yr
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
Chip Packaging Engineer 23-I
Mountain View, CA · On-site
$160K/yr
... package design tools. • Creating die and BGA symbols from scratch or from spreadsheet inputs • Setting up design environment, including tech files, stack ups, and constraints • Setting up ...
Chip Packaging Engineer 23-I
Mountain View, CA · On-site
$160K/yr
... package design tools. • Creating die and BGA symbols from scratch or from spreadsheet inputs • Setting up design environment, including tech files, stack ups, and constraints • Setting up ...
Packaging Design Engineer I
San Jose, CA · On-site
$72K/yr
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
Packaging Design Engineer I
San Jose, CA · On-site
$72K/yr
... package testing/qualification, and resolving packaging related issues. * Knowledge of packaging testing, design standards (ISO, Mil-spec, etc.), ASTM/ ISTA standards, transportation, and material ...
The candidate will work with package and IC designers to find ways to optimize the overall package design and perform system simulation to make sure all system level constraints are met prior to the ...
The candidate will work with package and IC designers to find ways to optimize the overall package design and perform system simulation to make sure all system level constraints are met prior to the ...
Advanced Packaging Engineer
Mountain View, CA · On-site
$200K - $350K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
Advanced Packaging Engineer
Mountain View, CA · On-site
$200K - $350K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
Advanced Packaging Engineer
$200K - $350K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
Quick apply
Advanced Packaging Engineer
$200K - $350K/yr
Use and develop AI-assisted tool flows to accelerate package design and signoff timelines What we're looking for * Exceptional abilities across the full advanced packaging design and tradeoffs * 10+ ...
TEMP Packaging Designer
San Francisco, CA · Hybrid
$45 - $55/hr
Support package design development for upcoming programs/launches on designated brands. Partner with product development and packaging teams to achieve the highest level of quality for each project ...
TEMP Packaging Designer
San Francisco, CA · Hybrid
$45 - $55/hr
Support package design development for upcoming programs/launches on designated brands. Partner with product development and packaging teams to achieve the highest level of quality for each project ...
Package Design information
See California salary details
$9.73 - $11.02
1% of jobs
$11.02 - $12.31
0% of jobs
$12.31 - $13.61
2% of jobs
$13.61 - $14.90
8% of jobs
$15.54 is the 25th percentile. Wages below this are outliers.
$14.90 - $16.20
27% of jobs
The median wage is $16.88 / hr.
$16.20 - $17.49
21% of jobs
$18.26 is the 75th percentile. Wages above this are outliers.
$17.49 - $18.78
25% of jobs
$18.78 - $20.08
6% of jobs
$20.08 - $21.37
3% of jobs
$21.37 - $22.67
1% of jobs
$22.67 - $23.96
4% of jobs
$9
$17
$23
How much do package design jobs pay per hour?
What is the difference between Package Design vs Graphic Designer?
| Aspect | Package Design | Graphic Designer |
|---|---|---|
| Credentials | Design degree or related certification | Design degree or related certification |
| Work Environment | Packaging companies, branding agencies, manufacturing | Advertising agencies, media companies, freelance |
| Industry Usage | Product packaging, branding, retail | Marketing materials, digital media, branding |
Package Design focuses on creating packaging solutions for products, emphasizing structural and visual aspects of packaging. Graphic Designers work on visual content across various media, including branding, advertising, and digital design. While both roles require design skills and similar credentials, Package Designers specialize in packaging materials and structures, whereas Graphic Designers have a broader scope in visual communication across multiple platforms.

Job description
Principal Photonics Package Architect
About the Role
Astera Labs is seeking a Principal Photonics Package Architect to define and drive package architecture for next-generation photonics products for scale up and scale out AI infrastructure applications. This is a high-impact senior individual contributor role focused on aligning electrical, thermal, and mechanical design requirements across functions, enabling robust package implementation, and guiding package technology decisions for NPO and CPO products.
Responsibilities
- Define photonics package architecture, define electrical and optical interface specifications, and establish signal integrity and power integrity requirements.
- Establish and manage Thermal Design Power (TDP) budgets and thermal performance targets.
- Drive cross-functional alignment with EIC, PIC, and hardware teams on co-design constraints and drive system optical link budget.
- Partner with validation, test, and reliability teams to define DFT and DFR requirements and acceptance criteria.
- Finalize bump map and ball map, and manage ECOs and revision control of package design databases.
- Lead package-level design reviews and own the package design technical roadmap.
Basic Qualifications
- B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field.
- 10+ years of experience in semiconductor or photonics package development, package design, or package integration, with demonstrated technical leadership.
- Strong understanding of package architecture tradeoffs across electrical, optical, thermal, mechanical, and manufacturability considerations.
- Experience working across chip, board, and system-level design electrical and optical interfaces in complex product development environments.
- Experience with package EDA tools and electrical simulation tools, including Cadence APD+ and Ansys HFSS.
- Experience with advanced packaging design, including 2.5D and 3D package architectures.
- Familiarity with package design flows, design database management, and engineering change control practices.
- Ability to drive technical decisions, resolve cross-functional issues, and communicate architecture direction clearly to stakeholders.
- Strong foundation in design reviews, risk assessment, and design quality from concept through production release.
Preferred Qualifications
- Experience with industry-standard optical interfaces and interconnect technologies relevant to package design.
- Experience with advanced photonics packaging technologies for data center interconnects.
- Experience supporting package bring-up and correlating design assumptions with validation results.
- Experience supporting cross-functional design closure with silicon, photonics, board, validation, test, and reliability teams.
- Knowledge of package design for NPO or CPO products.
About Astera Labs
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
11 - 50 Employees
Headquarters location
Santa Clara, CA, US
Year founded
2017