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Overnight Standard Cell Design Jobs (NOW HIRING)

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Placement & Optimization - Perform standard cell placement, legalization, and optimization to improve area, power, and timing. * Clock Tree Synthesis (CTS) - Design and optimize low-skew, high ...

GPU Physical Design PPA Engineer

Austin, TX · On-site

$134K - $138K/yr

... and drive standard cell and memory hard-IP offerings and recommend usage/methodology to the ... Experience with industry standard physical design tools. Experience with one or more of the ...

GPU Physical Design PPA Engineer

Austin, TX

$134K - $138K/yr

... and drive standard cell and memory hard-IP offerings and recommend usage/methodology to the ... Proficiency in logic design principles, physical design, power and timing concepts. Knowledge of ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically ...

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically ...

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Overnight Standard Cell Design information

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How much do overnight standard cell design jobs pay per hour?

As of Aug 15, 2026, the average hourly pay for overnight standard cell design in the United States is $17.05, according to ZipRecruiter salary data. Most workers in this role earn between $15.14 and $18.51 per hour, depending on experience, location, and employer.

What cities are hiring for Overnight Standard Cell Design jobs?

Cities with the most Overnight Standard Cell Design job openings:

What are the most commonly searched types of Standard Cell Design jobs?

The most popular types of Standard Cell Design jobs are:

What states have the most Overnight Standard Cell Design jobs?

States with the most job openings for Overnight Standard Cell Design jobs include:

Infographic showing various Overnight Standard Cell Design job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 77% Full Time, 18% Part Time, 3% Contract, and 1% Nights. Highlights an 95% Physical, 1% Hybrid, and 4% Remote job distribution, with an average salary of $35,463 per year, or $17 per hour.

Toolchain / Digital Design Engineer

SOUTHEASTERN CYBER LLC

Lincolnton, GA • On-site

$115K/yr

Part-time

Re-posted 19 days ago


Job description

Role Summary
Southeastern Cyber LLC is seeking a Digital Design / Toolchain Engineer to extend our proprietary toolchains and pipelines. The engineer will integrate various policies into an automated flow for system and hardware design.

Responsibilities
- Develop and extend EDA/RTL compilation tools and scripts (Python, C++, and/or Rust).
- Map quantified requirements into physical standard-cell routing and logic structures.
- Run synthesis, place-and-route, and area/power/timing (PPA) estimates to sweep architectural scaling limits (max model parameter count, max whitelist/blacklist size).
- Interface with the Principal Investigator and Hardware SME to ensure correct RTL generation and physical implementation.

Required Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
- Demonstrated expertise in EDA toolchains, RTL design (Verilog/SystemVerilog/VHDL), and digital logic synthesis.
- Strong scripting and automation skills for EDA flows.
- US Person (Citizen or Permanent Resident) eligible to work on defense-related technology.