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New Grad Asic Design Verification Engineer Jobs in Silver Spring, MD

BLN24

Business Analyst - Verification Engineer

Mclean, VA · On-site

$60K/yr

Business Analyst - Verification Engineer (QA) Company: BLN24 About Us: We find strength in teamwork ... Support human-level validations for Gen-AI led test-driven design processes. * Ensure AI-generated ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Peraton

Digital Design SME

Mclean, VA

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176 - $282/hr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in Silver Spring, MD

New Grad Asic Design Verification Engineer information

See Silver Spring, MD salary details

$109.1K

$154.2K

$172.6K

How much do new grad asic design verification engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for new grad asic design verification engineer in Silver Spring, MD is $154,188.00, according to ZipRecruiter salary data. Most workers in this role earn between $140,600.00 and $171,600.00 per year, depending on experience, location, and employer.

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

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New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in Silver Spring, MD as of June 2026, with employment types broken down into 82% Full Time, and 18% Contract. Highlights an 100% Remote job distribution, with an average salary of $154,188 per year, or $74.1 per hour.

[India] Senior UCIe Verification Engineer

EdgeCortix

Arlington, VA • On-site

$156K/yr

Full-time

Posted 18 days ago

Job description

Introduction

We are looking for a Senior UCIe Verification Engineer with strong experience in SystemVerilog/UVM-based verification of high-speed interconnects and SoC subsystems. The ideal candidate should have hands-on experience in verifying UCIe (Universal Chiplet Interconnect Express) IP and should have contributed to at least 1–2 successful SoC tape-outs. The role involves developing reusable verification environments, protocol compliance verification, subsystem/SoC integration, and driving verification closure.


About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Your Role and Responsibilities:

  • Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration.
  • Build reusable SystemVerilog/UVM verification environments from scratch.
  • Develop constrained-random and directed test scenarios to verify UCIe functionality and protocol compliance.
  • Verify UCIe protocol features, including:
      • Link initialization and training
      • Sideband communication
      • Adapter layer
      • Protocol layer
      • Data transfer and flow control
      • Link power management
      • Error detection and recovery
      • Reset and initialization sequences
  • Verify interoperability between UCIe and upper-layer protocols such as PCIe, CXL, or streaming interfaces.
  • Develop UVM agents, scoreboards, monitors, protocol checkers, and functional coverage models.
  • Write and debug SystemVerilog Assertions (SVA) for protocol compliance and interface checks.
  • Perform coverage analysis and drive functional and code coverage closure.
  • Debug RTL, protocol, and testbench issues using simulation and waveform analysis.
  • Support gate-level simulations, regression execution, and silicon bring-up activities.
  • Collaborate closely with architecture, RTL, DFT, firmware, physical design, and validation teams throughout the product development cycle.


Desired Qualifications:

  • 6–12 years of experience in functional verification using SystemVerilog and UVM.
  • Strong experience in developing complete UVM verification environments from scratch.
  • Good understanding of UCIe architecture and protocol.
  • Experience verifying high-speed serial interfaces or chiplet interconnects.
  • Strong understanding of:
     • AXI4
     • High-speed protocol verification
     • Clock domain crossings (CDC)
     • Reset domain crossings (RDC)
     • Protocol compliance verification
  • Experience with constrained-random, assertion-based, and coverage-driven verification methodologies.
  • Strong experience writing SystemVerilog Assertions (SVA).
  • Experience with gate-level simulation and timing-aware verification.
  • Excellent RTL and protocol debugging skills.
  • Experience in verifying die-to-die interfaces or chiplet-based architectures.
  • Experience with subsystem and SoC-level verification.
  • Experience with emulator-based verification platforms.
  • Exposure to Formal Verification techniques.
  • Familiarity with Continuous Integration (CI/CD) tools such as Jenkins or GitLab CI.
  • Experience with scripting languages such as Python, Perl, or Tcl.
  • Experience with version control systems such as Git.
  • SoC Experience
     • Hands-on experience in 1–2 successful SoC tape-outs.
     • Experience integrating UCIe subsystems into complex SoCs.
     • Exposure to boot flows, clock/reset architecture, power management, and chiplet integration.
     • Experience collaborating with firmware and post-silicon validation teams during bring-up and debug.

What’s in it for you?

Make a difference: you will have the opportunity to join a well-funded fabless AI semiconductor startup that is disrupting the AI software and hardware co-design space. Be an integral part of its growth and momentum.

Benefits and Perks

  • Highly competitive salary and stock options
  • Flex work time
  • Top-tier employee benefits