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New Grad Asic Design Verification Engineer Jobs in Edmonds, WA

Design Verification Engineer

Seattle, WA · On-site

$175 - $308.50/hr

  • Medical

  • Dental

  • Retirement

At Apple, our new ideas have a way of becoming great products, services, and customer experiences ... Design Verification Engineers at Apple are responsible for verifying the functionality and ...

Design Verification Engineer

Seattle, WA

$122K - $184K/yr

  • Medical

  • Dental

  • Retirement

At Apple, our new ideas have a way of becoming great products, services, and customer experiences ... Design Verification Engineers at Apple are responsible for verifying the functionality and ...

FPGA/ASIC Design Engineer (Silicon Engineering)

Redmond, WA · On-site

$145K - $195K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... verification. * Collaborate with software engineers in developing production software for your ... Enjoys being challenged and learning new skills * Master's in Electrical/Computer Engineering or ...

FPGA/ASIC Design Engineer (Silicon Engineering)

Redmond, WA · On-site

$145K - $195K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... verification. * Collaborate with software engineers in developing production software for your ... Enjoys being challenged and learning new skills * Master's in Electrical/Computer Engineering or ...

Senior ASIC Design Engineer - Terawave

Seattle, WA · On-site

$230K - $322K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin ... Formal verification * Functional coverage, definition and collection * Module verification

Senior ASIC Physical Design Engineer

Seattle, WA

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

... verification, and packaging teams. You'll be a key contributor in achieving timing closure ... In your first 6 months, you will develop and implement new SoC sub-systems for satellite ...

Senior FPGA Prototyping Engineer

Seattle, WA · On-site

$120K - $225K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Collaborate closely with ASIC Design, Verification, Firmware, Software, Systems, and DFT teams to accelerate product development. Qualifications * BS or MS in Electrical Engineering, Computer ...

Principal ASIC Package Design Engineer

Seattle, WA · On-site

$200 - $280/hr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package ...

Showing results 21-40

New Grad Asic Design Verification Engineer information

See Edmonds, WA salary details

$115.9K

$163.8K

$183.4K

How much do new grad asic design verification engineer jobs pay per year?

As of Aug 17, 2026, the average yearly pay for new grad asic design verification engineer in Edmonds, WA is $163,786.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,300.00 and $182,300.00 per year, depending on experience, location, and employer.

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What cities near Edmonds, WA are hiring for New Grad Asic Design Verification Engineer jobs?

Cities near Edmonds, WA with the most New Grad Asic Design Verification Engineer job openings:

Infographic showing various New Grad Asic Design Verification Engineer job openings in Edmonds, WA as of July 2026, with employment types broken down into 83% Full Time, 14% Part Time, and 3% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $163,786 per year, or $78.7 per hour.

Design Verification Engineer

Apple Inc.

Seattle, WA • On-site

$175 - $308.50/hr

Other

Medical, Dental, Retirement

Re-posted 10 days ago


Apple rating

8.0

Company rating: 8.0 out of 10

Based on 677 frontline employees who took The Breakroom Quiz

7th of 30 rated technology retailers


Job description

Seattle, Washington, United States Hardware

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us.

Description

As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all fields (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- Neural Engine hardware
- DRAM subsystem, memory controller logic
- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- Hardware security, including cryptographic algorithm implementations
- High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- Power management and fabric infrastructure
- Memory cache management
- Display Subsystem for variety of panels and products
These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It’s up to you!

Minimum Qualifications
  • Minimum of BS + 10 years relevant industry experience.
Preferred Qualifications
  • Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
  • Knowledge of SystemVerilog, digital simulation and debug
  • Knowledge of computer architecture and digital design fundamentals
  • Good SW programming skills with knowledge of data structures and algorithms
  • Experience with Python, Perl, or similar scripting language
  • Ability to work independently to deliver the project goals
  • Knowledge of verification methodologies like UVM
  • Experience with C/C++, assembly is a plus.
  • Excellent interpersonal and communication skills and the dream to take on diverse challenges.
Compensation and Benefits

Apple offers a base pay of $175,000 to $308,500, based on skills, qualifications, experience, and location. Apple employees are also eligible for discretionary employee stock programs, including restricted stock unit awards and participation in the Employee Stock Purchase Plan. Benefits include comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and tuition reimbursement for formal education related to advancing your career. This role may also be eligible for discretionary bonuses or commission payments and relocation assistance.

Apple accepts applications to this posting on an ongoing basis.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple believes accessibility is a fundamental human right and strives to reflect this in all aspects of its culture, benefits and digital tools. Learn about accessibility in Apple’s workplace. Learn about reasonable accommodations for job applicants.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976