Santa Clara, CA · Hybrid
$196K/yr
We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs. You should have ...
Santa Clara, CA · Hybrid
$196K/yr
We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs. You should have ...
Santa Clara, CA · On-site
$196K/yr
We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs. You should have ...
Santa Clara, CA · On-site
$196K/yr
We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs. You should have ...
We are looking for an Implementation Methodology Engineer to join NVIDIA VLSI team. If you are looking for a challenging and exciting role and you are a self-starter and highly motivated individual ...
We are looking for an Implementation Methodology Engineer to join NVIDIA VLSI team. If you are looking for a challenging and exciting role and you are a self-starter and highly motivated individual ...
Santa Clara, CA · On-site
$153K - $229K/yr
About the Role As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state-of-the-art design analytics platform. Your work will have a consequential ...
Santa Clara, CA · On-site
$153K - $229K/yr
About the Role As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a state-of-the-art design analytics platform. Your work will have a consequential ...
Santa Clara, CA · On-site
$145K - $191K/yr
We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined ...
Santa Clara, CA · On-site
$145K - $191K/yr
We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined ...
$145K - $191K/yr
We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined ...
$145K - $191K/yr
We are now looking for a DFT Methodology Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined ...
We are looking for an Implementation Methodology Engineer to join NVIDIA VLSI team. If you are looking for a challenging and exciting role and you are a self-starter and highly motivated individual ...
We are looking for an Implementation Methodology Engineer to join NVIDIA VLSI team. If you are looking for a challenging and exciting role and you are a self-starter and highly motivated individual ...
San Diego, CA · On-site
$140K - $210K/yr
Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms of various configurations * Cross-site collaboration ...
San Diego, CA · On-site
$140K - $210K/yr
Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms of various configurations * Cross-site collaboration ...
San Francisco, CA · On-site
$149K - $196K/yr
They are seeking a Senior Product Manager for the Methodology team to define the vision and strategy for data artifacts, manage verifier partnerships, and ensure methodologies are accurate and ...
San Francisco, CA · On-site
$149K - $196K/yr
They are seeking a Senior Product Manager for the Methodology team to define the vision and strategy for data artifacts, manage verifier partnerships, and ensure methodologies are accurate and ...
This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. You will lead aggressive PPA optimization campaigns and invent next ...
This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. You will lead aggressive PPA optimization campaigns and invent next ...
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you will contribute to the development of next-generation FPGA products. In this role, you will help ...
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you will contribute to the development of next-generation FPGA products. In this role, you will help ...
This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. You will lead aggressive PPA optimization campaigns and invent next ...
This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. You will lead aggressive PPA optimization campaigns and invent next ...
San Francisco, CA · On-site
$187K - $227K/yr
Own the roadmap for Watershed's corporate methodology: define the vision, strategy, and north‑star metrics for our data artifacts that constitute methodology (ingestion templates, activity types ...
San Francisco, CA · On-site
$187K - $227K/yr
Own the roadmap for Watershed's corporate methodology: define the vision, strategy, and north‑star metrics for our data artifacts that constitute methodology (ingestion templates, activity types ...
... methods. Principal Duties & Responsibilities: • Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block ...
... methods. Principal Duties & Responsibilities: • Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block ...
San Jose, CA · On-site
$124K/yr
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you will contribute to the development of next-generation FPGA products. In this role, you will help ...
San Jose, CA · On-site
$124K/yr
Join our leading-edge RTL Design Methodology team as a Hardware Development Engineer , where you will contribute to the development of next-generation FPGA products. In this role, you will help ...
$122K - $168K/yr
Are you excited to build the automation infrastructure behind next-generation silicon design? We're seeking a Senior VLSI Methodology Engineer to join our team and to design automation that powers ...
$122K - $168K/yr
Are you excited to build the automation infrastructure behind next-generation silicon design? We're seeking a Senior VLSI Methodology Engineer to join our team and to design automation that powers ...
San Jose, CA · On-site
$124K/yr
Develop new IPs and methodologies, including process characterization IP (timing, defectivity etc.) for test-vehicles * Define DFx Architecture for AMD's next generation monolithic and stacked SoC ...
San Jose, CA · On-site
$124K/yr
Develop new IPs and methodologies, including process characterization IP (timing, defectivity etc.) for test-vehicles * Define DFx Architecture for AMD's next generation monolithic and stacked SoC ...
San Jose, CA · On-site
$145K/yr
AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you ...
San Jose, CA · On-site
$145K/yr
AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you ...
AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you ...
AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you ...
Santa Clara, CA · On-site
$122K - $168K/yr
Are you excited to build the automation infrastructure behind next-generation silicon design? We're seeking a Senior VLSI Methodology Engineer to join our team and to design automation that powers ...
Santa Clara, CA · On-site
$122K - $168K/yr
Are you excited to build the automation infrastructure behind next-generation silicon design? We're seeking a Senior VLSI Methodology Engineer to join our team and to design automation that powers ...
| Aspect | Methodology | Data Analyst |
|---|---|---|
| Required credentials | Often no formal credentials, but familiarity with research methods and frameworks | Bachelor's degree in statistics, data science, or related field; certifications like CAP or Microsoft Certified Data Analyst |
| Work environment | Designing research approaches, frameworks, and processes; often in research, consulting, or academic settings | Analyzing data sets, creating reports, and visualizations; in corporate, finance, healthcare, or tech industries |
| Employer and industry usage | Used by researchers, consultants, and project managers to structure investigations | Employed by companies across industries to interpret data and support decision-making |
While Methodology focuses on designing research frameworks and approaches, Data Analysts apply these methods to interpret data and generate insights. Both roles are essential in research and data-driven environments, but Methodology is more about planning, whereas Data Analysts execute data analysis tasks.
9.6
Based on 17 frontline employees who took The Breakroom Quiz
8th of 245 rated software companies
NVIDIA's success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design.
We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and below) and high performance GPU, CPU and SoC designs. You should have deep, handson experience across the full RTL2GDS flow, with expertise in key stages such as RTL, DFT, synthesis, placement, optimization, CTS, routing, and signoff. Creativity and self-drive to explore is required. Our engineers enjoy unusually high intellectual freedom and the ability to explore broad roles. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, it does not get any better than this!
What you'll be doing:
Working directly with core P&R engine developers to define realworld optimization problems, shape requirements and roadmaps, and provide detailed feedback on engine behavior, QoR, and scalability.
Defining and rolling out nextgen flows, including refactoring legacy flows and consolidating adhoc solutions into scalable, maintainable frameworks used across multiple design teams.
Designing and running rigorous A/B and multivariant experiments to compare flows, engines, and tool settings. Developing Pythonbased analytics and ML/GenAI techniques to mine large QoR datasets, recommend flow settings, and automate analysis.
Performing deep rootcause analysis on QoR issues across engines, tools, and flows, and driving methodologies to resolve the 'long tail' of timing closure and performance limiters.
Partnering with architecture, RTL, DFT, synthesis, physical design, power, signoff, and CAD/methodology teams as a key technical leader and bridge.
Driving aggressive PPA and schedule targets and the adoption of new tools and flows across the company.
What we need to see:
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
8+ years physical design experience, with deep expertise in industry standard tools like ICC2/Innovus, PrimeTime/Tempus, etc.
Extensive handson P&R experience taking complex blocks or chips to tapeout with aggressive PPA targets.
Proven skills in Python, Perl, and TCL flow development.
Strong problemsolving skills and selfmotivation, demonstrated by simplifying complex, cluttered environments and modernizing legacy tools and processes.
Excellent communication and collaboration skills, with a track record of driving consensus and solving complex issues across distributed design, CAD, and R&D teams.
Ways to stand out from the crowd:
Experience collaborating with EDA or internal R&D teams on core engine development, codefining features, developing benchmarks and leading validation and deployment.
Expertise in designing and automating A/B tests and largescale regressions, and analyzing large QoR datasets to understand trends and drive rootcause analysis.
Background in advancednode and largescale designs with exposure to advancednode challenges (DFM, variability, EM/IR, power integrity).
Handson experience applying AI/ML or GenAI to physical design, QoR analysis, or flow development will be a strong plus.
If working handson from early architecture and RTL through silicon, and serving as the connector between core developers, methodology teams, and users, excites you, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993
