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Memory Verification Engineer Jobs (NOW HIRING)

Vings Technologies

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

SV/UVM; memory controller/subsystem DV; coverage & debug Role Summary We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within ...

New

NVIDIA Corporation

NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people ...

New

Nvidia

ASIC Verification Engineer

Santa Clara, CA · Hybrid

As a Verification Engineer at NVIDIA, you will be responsible for verifying the design ... Prior verification experience related to high speed IO protocols, or memory coherence is a big plus ...

Nvidia

ASIC Verification Engineer

Santa Clara, CA · Hybrid

Define the verification scope, and contribute to the development of the verification infrastructure for memory subsystem units * Collaborate with architects, designers, software engineers across ...

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Memory Verification Engineer information

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$80K

$142.6K

$203.5K

How much do memory verification engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for memory verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Memory Verification Engineer vs Memory Design Engineer?

AspectMemory Verification EngineerMemory Design Engineer
Primary FocusVerifying memory modules and ensuring functionality and reliabilityDesigning and developing memory architectures and circuits
Skills & CertificationsKnowledge of verification tools, scripting, and memory protocolsExpertise in circuit design, EDA tools, and memory architecture
Work EnvironmentTesting labs, simulation environments, verification teamsDesign teams, R&D labs, hardware development
Industry UsageSemiconductor companies, hardware firms, verification service providersSemiconductor companies, chip design firms, hardware manufacturers

Memory Verification Engineers focus on testing and validating memory modules to ensure they meet specifications, while Memory Design Engineers develop the actual memory architectures and circuits. Both roles require knowledge of memory technologies, but verification emphasizes testing and validation, whereas design emphasizes creation and development.

What cities are hiring for Memory Verification Engineer jobs?

Cities with the most Memory Verification Engineer job openings:

What are popular job titles related to Memory Verification Engineer jobs?

For Memory Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Memory Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 93% Full Time, 3% Part Time, and 4% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Design Verification Engineer

San Jose, CA • On-site

Vings Technologies
IT Services • 11 - 50 employees
Learn more about Vings Technologiesexternal

$159K - $194K/yr

Other

Posted 3 days ago

New

Job description

Role: Design Verification Engineer
Location: San Jose, CA - Onsite
Experience: 8+ years
Mandatory Skills: HBM2E/HBM3/HBM3E hands-on verification; SV/UVM; memory controller/subsystem DV; coverage & debug
 
Job Description:
 
Role Summary
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
Key Responsibilities:
·       Develop and maintain UVM-based verification environments
·       Create test plans, testcases, and coverage models
·       Perform functional verification of RTL designs
·       Debug RTL and testbench issues
·       Drive coverage closure (functional + code)
 
Required Skills:
 
·       Strong hands-on with System Verilog and UVM
·       Experience in block-level verification
·       Good understanding of digital design fundamentals
·       Experience with debug tools (Verdi, DVE, etc.)
 
Good to Have:
·       Exposure to low-power verification (UPF)
·       Experience with AMBA protocols (AXI/AHB/APB)

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