As a Senior/Staff GPU Design Verification Engineer - Subsystems, you will contribute to the ... Knowledge of memory subsystem or coherent interconnects is a plus.* Experience with performance ...
As a Senior/Staff GPU Design Verification Engineer - Subsystems, you will contribute to the ... Knowledge of memory subsystem or coherent interconnects is a plus.* Experience with performance ...
Role and Responsibilities As a Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Role and Responsibilities As a Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Formal Verification ... Knowledge of memory subsystem or coherent interconnects is a plus. * Proficiency in constrained ...
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Formal Verification ... Knowledge of memory subsystem or coherent interconnects is a plus. * Proficiency in constrained ...
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Formal Verification ... Knowledge of memory subsystem or coherent interconnects is a plus. * Proficiency in constrained ...
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Formal Verification ... Knowledge of memory subsystem or coherent interconnects is a plus. * Proficiency in constrained ...
Role and Responsibilities As a Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Role and Responsibilities As a Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Principal PCIe Subsystem Verification Engineer
Austin, TX · On-site
$249K - $338K/yr
New team members will join hands with other Architects, RTL design and verification engineers ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Principal PCIe Subsystem Verification Engineer
Austin, TX · On-site
$249K - $338K/yr
New team members will join hands with other Architects, RTL design and verification engineers ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Principal PCIe Subsystem Verification Engineer
Austin, TX · Hybrid
$249K - $338K/yr
As a creative verification engineer with a knowledge of Sub-System integration verification, IO ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Principal PCIe Subsystem Verification Engineer
Austin, TX · Hybrid
$249K - $338K/yr
As a creative verification engineer with a knowledge of Sub-System integration verification, IO ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Senior Staff Engineer, GPU Design Verification (Subsystems)
San Jose, CA · On-site
$121K - $164K/yr
Role and Responsibilities As a Senior Staff GPU Design Verification Engineer - Subsystems, you will ... Knowledge of memory subsystem or coherent interconnects is a plus. * Experience with performance ...
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Principal Design Verification Engineer - High Performance CPU Subsystem
Santa Clara, CA · On-site
$159K/yr
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Principal Design Verification Engineer - High Performance CPU Subsystem
Santa Clara, CA · On-site
$159K/yr
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$150K - $277K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$150K - $277K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$150K - $277K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$150K - $277K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
Principal Design Verification Engineer - High Performance CPU Subsystem
Austin, TX · On-site
$134K - $164K/yr
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Principal Design Verification Engineer - High Performance CPU Subsystem
Austin, TX · On-site
$134K - $164K/yr
Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior ... engineers, influencing methodology, and driving cross-team execution on complex verification ...
Wireless Radio Verification Engineer
San Diego, CA · On-site
$144K/yr
As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... You'll own subsystem verification from test planning through coverage closure, building testbench ...
Wireless Radio Verification Engineer
San Diego, CA · On-site
$144K/yr
As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... You'll own subsystem verification from test planning through coverage closure, building testbench ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
Graphics Cache Hierarchy Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
The Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects ...
SoC Architect, Memory Subsystem
San Jose, CA · On-site
$124K - $208K/yr
... verification plans. * Stay up-to-date with emerging memory technologies and recommend their ... Joining our team means collaborating alongside talented engineers from diverse technical ...
SoC Architect, Memory Subsystem
San Jose, CA · On-site
$124K - $208K/yr
... verification plans. * Stay up-to-date with emerging memory technologies and recommend their ... Joining our team means collaborating alongside talented engineers from diverse technical ...
SoC Architect, Memory Subsystem
San Jose, CA · On-site
$124K - $208K/yr
... verification plans. * Stay up-to-date with emerging memory technologies and recommend their ... Joining our team means collaborating alongside talented engineers from diverse technical ...
SoC Architect, Memory Subsystem
San Jose, CA · On-site
$124K - $208K/yr
... verification plans. * Stay up-to-date with emerging memory technologies and recommend their ... Joining our team means collaborating alongside talented engineers from diverse technical ...
SoC Memory Subsystem Architect
Sunnyvale, CA · On-site
$196K/yr
Work with Hardware design, verification, emulation, and validation teams to build and test the ... Master or PhD in Electrical or Computer Engineering. * Excellent communication skills in both ...
SoC Memory Subsystem Architect
Sunnyvale, CA · On-site
$196K/yr
Work with Hardware design, verification, emulation, and validation teams to build and test the ... Master or PhD in Electrical or Computer Engineering. * Excellent communication skills in both ...
Memory Subsystem Verification Engineer information
See salary details
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
How much do memory subsystem verification engineer jobs pay per year?
What is the difference between Memory Subsystem Verification Engineer vs Memory Validation Engineer?
| Aspect | Memory Subsystem Verification Engineer | Memory Validation Engineer |
|---|---|---|
| Primary Focus | Verifying memory subsystem design correctness through simulation and testing | Validating memory modules and systems in real-world scenarios |
| Skills & Certifications | Hardware verification, scripting, knowledge of memory architectures | Memory testing, validation tools, quality assurance |
| Work Environment | Design labs, simulation environments, hardware testing labs | Field testing, lab environments, customer sites |
While both roles involve working with memory technologies, the Memory Subsystem Verification Engineer focuses on verifying the design and functionality of memory subsystems during development. In contrast, the Memory Validation Engineer tests and validates memory modules in real-world conditions to ensure quality and performance before deployment.
What are popular job titles related to Memory Subsystem Verification Engineer jobs?
For Memory Subsystem Verification Engineer jobs, the most frequently searched job titles are:

Staff Engineer, GPU Design Verification (Subsystems)
On-site
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 10 days ago
Key responsibilities
Contribute to the verification strategy and execution for GPU subsystems by developing verification plans, goals, coverage metrics, and sign-off criteria.
Design, develop, and maintain scalable verification testbenches using SystemVerilog, UVM, and C++, and apply various verification techniques to validate subsystem behaviors.
Assist with debugging, analyzing failures, and collaborating with design and architecture teams to ensure verification aligns with architectural intent and system-level requirements.